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Possible False Triggers on One Card 2 jbell 22 Thu May 16, 2013 3:40 pmjbell
High speed + low speed data on the same card. 4 jbell 98 Thu Apr 11, 2013 4:57 pmjbell
Input FIFO overrun 5 jbell 134 Wed Feb 20, 2013 4:06 pmjhenderson
Loading .bit file with VsProm 3 jbell 253 Tue Oct 30, 2012 8:11 amjhenderson
Accessing External Trigger From BSP on X5-G12 1 , 2 ] 23 jbell 1156 Mon Oct 22, 2012 4:05 pmjhenderson
Loading Bit Stream in ePC with X5-G12 7 jbell 523 Mon Sep 10, 2012 4:07 pmjbell
several questions about external trigger for X5-G12 1 surewin 194 Fri Sep 07, 2012 2:34 pmrvanbuskirk
X5-G12 A/D0 and A/D1 seem to be disabled 1 , 2 ] 24 anwokafor 1128 Mon Jul 23, 2012 1:21 pmbjackson
Trigger delay 1 anwokafor 212 Thu Jun 28, 2012 2:06 pmjhenderson
2GSPS for X5-G12 sampling rate 3 surewin 729 Thu Jun 14, 2012 1:50 pmjhenderson
2 X5-G12 acquire data with C++ 1 , 2 ] 24 rvanbuskirk 1431 Tue May 08, 2012 10:17 amrvanbuskirk
X5-G12: Snap example 3 ARNAUD 488 Thu Nov 10, 2011 3:41 amjhenderson
Question of X5-G12 ADC control !! 9 rafle1806 692 Mon Oct 24, 2011 1:52 pmbjackson
Question abot ADC setting 13 hank 962 Fri Oct 07, 2011 2:11 amjhenderson
X5-G12: Manage data of 1 channel at 2GSPS under BSP 2 ARNAUD 561 Wed Aug 10, 2011 9:44 ambkao
Regarding the signal level of P15 on X5-G12 1 rafle1806 564 Fri Aug 05, 2011 10:34 amdmclane
A question about sequence of AC timing? 3 rafle1806 589 Thu Jul 21, 2011 9:36 amjhenderson
How to access via Wishbone bus? (SUREWIN Technology) 1 rafle1806 571 Thu Jun 02, 2011 9:24 amPat Carr
Could you help to deliver ver-B bit file? 1 hank 615 Fri May 06, 2011 10:20 amPat Carr
register read/write via PC software 4 surewin 923 Fri Apr 15, 2011 1:37 pmjhenderson
Clock limits 0 jhenderson 570 Thu Jan 27, 2011 1:57 pmjhenderson
Access to the "ii_ads5400_phy_top" vhdl code 1 pedroLauSemedo 643 Wed Dec 01, 2010 9:08 amsmoses
64 bit support on Malibu data logging software 3 pedroLauSemedo 741 Wed Nov 24, 2010 11:16 amjhenderson
X5-G12 VHDL simulation gets stuck on register pooling op. 3 pedroLauSemedo 748 Thu Oct 28, 2010 7:29 amsmoses
PLL to FPGA routing 0 jhenderson 721 Tue Mar 23, 2010 6:34 amjhenderson
Single-sided input range? 1 jhenderson 713 Wed Jan 20, 2010 8:59 amjherring
bug report 14 mmwillis 1969 Mon Nov 09, 2009 5:38 ammmwillis
BinView autorefresh, still not working 3 mmwillis 1031 Sat Oct 31, 2009 4:08 pmjhenderson
AC/DC coupled inputs and Integrated FFT 1 potsaid 849 Fri Oct 23, 2009 4:44 pmPat Carr
Trigger voltage levels 0 jhenderson 767 Tue Jul 21, 2009 9:33 amjhenderson
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