Framework Logic User Guide?

BrandonJ · Joined: 14 Apr 2006 Posts: 45 Location: Washington, DC

I'm reading through the Velocia PMC Manual to find out about the user logic for the UWB. Under the UWB chapter I found:

jhenderson · Posted: Tue May 23, 2006 5:35 pm Post subject: Velocia PMC manual

Available at http://www.innovative-dsp.com/support/manuals/Velocia_PMC_Manual.pdf

BrandonJ · Joined: 14 Apr 2006 Posts: 45 Location: Washington, DC

Is there something more detailed, such as describing the default logic data flow and signals of importance? That document is fairly high level and mostly talks about the PCI data flow.

Thanks,
-Brandon

BrandonJ · Joined: 14 Apr 2006 Posts: 45 Location: Washington, DC

Ah, nevermind. I see there is a section on the UWB later in the manual that addresses some of these things.

BrandonJ · Joined: 14 Apr 2006 Posts: 45 Location: Washington, DC

Section 5.2.1 mentions that the A/D RF input is differential, so I assume the digital output is differential (A,B)?

The following top-level instance contains signals connected to top-level ports in the Framework logic for A/D 0:

inst_ad0 : ii_pmc_uwb_adc
port map(
-- ...
fs_a => adc0_clk_a,
fs_b => adc0_clk_b,
adc_da => adc0_da,
adc_db => adc0_db,
dout => ad_data0,
-- ...
);

Please clarify the A and B notation.

In the current application this vhdl module appears to pack the data into a 32-bit word, which is then asynchronous fifo'ed, with the B input in the MSB and A input in the LSB with an overrage bit and junk.

If I want single ended data can I just nab either the A or B inputs and ignore the other?

What other logic is non-essential and only part of the example applications? It appears that I can start using data after the fifo output registers (ad_reg0, ad_reg1). Do I then just connect my user application to the packetizer front end?

Thanks

edziedzic · Joined: 24 May 2006 Posts: 8

The digital data is not differential. In order to minimize the data bandwidth the A/D manufacturor provides the data on two buses running at half the sample rate. The two clocks are 180 deg out of phase and are used to sample these buses (a,b).

If you want to place a user defined function in the FPGA, place it between the A/D component and the packetizer.

BrandonJ · Joined: 14 Apr 2006 Posts: 45 Location: Washington, DC

Ok, thanks.

In the Framework default logic the 'sys_clk' is connected every sequential block, aside from the ad sample clocks in 'inst_ad0' and 'inst_ad1'. I didn't see any reference to the sys_clk input port other than Illustration 10, which says that it is 100 MHz. Is this provided on the pcb?. Is it suitable for input into a DCM to upconvert to a higher frequency?

edziedzic · Joined: 24 May 2006 Posts: 8

Yes. and yes.

BrandonJ · Joined: 14 Apr 2006 Posts: 45 Location: Washington, DC

edziedzic · Joined: 24 May 2006 Posts: 8

Following the A/D component are two functional blocks: an offset/gain correction, and a stacker FIFO. Information for these is contained in Framework. One would think that your user function would follow the offset/gain correction & before the data is stacked.

No plans for a user wrapper as of yet.

BrandonJ · Joined: 14 Apr 2006 Posts: 45 Location: Washington, DC

Offset/Gain Correction:
Is there any reason the input data is sign extended from 12-bit to 14-bit and then corrected to 14-bit. I.e, is the output result bound between the 12 LSBs or does this block utilize all 14-bits because of gain in that block?

Sorry for all the questions... I appreciate it.

-Brandon

edziedzic · Joined: 24 May 2006 Posts: 8

The output is a sign extended 12-bit value.