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amane
Joined: 17 Apr 2006
Posts: 118
Location: Simi Valley
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 Posted: Thu May 14, 2009 3:57 pm Post subject: How many user IOs available on duet ! |
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Q: How many user IO pins are available on Duet ?
Ans :
1. Duet has 1 Virtex2Pro (VP40) user FPGA
This FPGA is connected to PMC j4 connector.
So there are 64 pins available on J4 connector from user FPGA.
Also few reserved pins on PMC connectors are hooked up to user FPGA.
There are 8 reserved pins hooked up to J2 connector.
On the XMC connector there are 6 pins connected from the user FPGA.
On PXI interface there are 24 IO pins hooked from the user FPGA along with 8 trigger ports. |
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neurotech
Distributor
Joined: 28 Apr 2006
Posts: 2
Location: Singapore
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| Posted: Thu May 14, 2009 9:11 pm Post subject: Re: How many user IOs available on duet ! |
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| amane wrote: | Q: How many user IO pins are available on Duet ?
Ans :
1. Duet has 1 Virtex2Pro (VP40) user FPGA
This FPGA is connected to PMC j4 connector.
So there are 64 pins available on J4 connector from user FPGA.
[Mostafa] Do you mean JN4 connector page 198 of User Manual?
Also few reserved pins on PMC connectors are hooked up to user FPGA.
[ Mostafa] are you referring to J2 below or it is something else?
There are 8 reserved pins hooked up to J2 connector.
[ Mostafa] are you referring to CJ2 page 212-216 of User Manual, it is PXI connector? Totally 38 pins of FPGA are connected to this connectors A1 - A3, A16-A21, B2, B16, B18-B21 and C1 .C3, C18-C21, D1-D3, D15-D21, E1-E3, E15-E21, Am I right?
On the XMC connector there are 6 pins connected from the user FPGA.
[Mostafa] are you referring to P1-XMC pages 210-211 ? Could you specify wich pins are connected to FPGA?
On PXI interface there are 24 IO pins hooked from the user FPGA along with 8 trigger ports. |
[ Mostafa] Have repeated J2 ( CJ2) above ? Where are those 24 pins?
If you provide a schematic diagram will be more clear |
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jhenderson
Site Admin
Joined: 07 Mar 2006
Posts: 2267
Location: So. Cal. USA
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| Posted: Fri May 22, 2009 8:17 am Post subject: Schematic excerpt |
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| A schematic excerpt has been emailed to you |
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