Adding register to System Configuration

[lkremer]

Is is possible to add additional control and status registers to the "System Configuration" Simulink block in the X5-400m-lib?

I read in the Framework Logic User Guide how it is possible using VHDL. I don't know how to go about doing the same in Simulink.

Registers 36 through 43 appear to be unused. Is this correct? The additional 8 registers would be useful in my design.

Is there another way, other than modifying the System Configuration block, to create additonal registers?

[amane]

Hi,
The default BSP provides registers 44--47 as general purpose registers.
Since each application have a different requirement for number of registers , BSP provides bare minimum value selected as a design criteria.

If you need to add extra registers, here is some suggestions

1. use nonmemory mapped (nmm) gateways to add extra register.

2. generate a ngc netlist using nmm gateways

3. These gateways appear as ports in the ngc netlist.

3. add these extra ports in the ngc netlist component in the top file
e.g. (x5_400m_implement in the top file)

4. hook up the extra ports to appropriate command bus registers

5. Compile the design under ISE env to get a standalone image for the FPGA


Sincerely,
Amit Mane
System Engineer
Innovative Integration Inc
Simi Valley,Ca 93065

[lkremer]

Could you give me a little more help with adding a nonmemory mapped gateways and generating the netlist?

I see nonmemory mapped (nmm) blocks used inside the II models, but I haven't found "nmm" in any of the libraries. Is a "nmm" just a Xilinix Gateway In block?

Where do I make the connectionto the Wishbone System Bus and how do I specify the address?

[jhenderson]

I can suggest following 2 ways to get the job done.....

1. Using register 44 and 45

In this case no changes in the BSP are needed to have additional registers.

Register 44 will be used to specify the address and 45 will be used to
specify the data. A separate vhdl code (I name it as cmd_bus_decode.vhd) need to be added as a black box in Simulink model.

Adding vhdl code as a black box is explained in the System Gnereator
manual in details. There is seperate chapter named ""Importing HDL
Modules""

bits 2..0 of register 44 will be used to specify the address of the
additional registers
bits 31..0 of register 45 will be used to specify the data.
cmd_bus_decode will implement a demux to write data into 8 separate
registers depending on the address specified in register 44 bits (2..0)
By using this scheme you can implement any number of registers (upto 2^32)

Advantages : Writing only one vhdl file is sufficient to implement any
number of registers( upto 2^32)
No additional change in BSP is needed

2. Adding register using (memory mapped) gateways in Simulink model
In this case, a number of extra mm gateways are added in the logic (One
for each register)
Then generate a ngc netlist with these extra gateways.
As a result of compilation, a your design_name.vhd is created
This file will have extra inputs (mm gateways specified in the mdl file) .
Hook up these gateways to appropriate ctl_reg inputs of your choice in
the x5_400m_top vhd file
Compile under ISE to get the stand alone bit image