Synchronization problem using external trigger

[AQAV]

Dear Supporter,

We are using four X5-400M boards in parallel. But we find synchronization problems between boards, even with one standalone board.

An external trigger signal synchronized with the ADC sampling clock (400MHz) is used for synchronization. The problems we encounter are:

1- If we run SNAP and do data storage several times using external trigger, for one board, the initial phases of two ADCs' outputs are not constant and change from one measurement to another.

2- When the same trigger signals and signals are send to different boards, the sampled data are also different in phases from different boards.

The voltage level for trigger signal is 2V.

Do you have any tips of suggestions to solve the problems described? Thanks in advance.

[jherring]

There are several things to check:

1) You mention that your trigger signal is 2V. Remember that the X5-400M trigger input is LVTTL 50 ohm terminated. The minimum low level is 0.8V, and the minimum high level is 2.0 V. Please check your trigger signal to make sure the source can drive these levels into a 50 ohm load.

2) Edge rate of the trigger signal is critical if single-sample accuracy is to be maintained. The edge must transition in less than one sample period for the trigger to be deterministic. If the trigger signal is slower than this the trigger point may move with respect to the input signal.

3) Make sure the trigger signal is clean of undershoot and overshoot. Any transition outside the legal voltage levels may cause the trigger input to malfunction. Check for undershoot/overshoot (as well as the edge rate mentioned above) with a very short (1/4" to 1/2") ground lead connected to the barrel of a properly compensated oscilloscope probe.

Please note that the logic on the X5-400M acquires data on a 200 MHz DDR clock from the A/Ds and so is limited to dual sample resolution when referencing to external trigger signals.

[AQAV]

Thanks a lot for the reply.

Following the suggestions, we increased the trigger signal voltage to 2.7V, and checked the edge rate, undershoot and overshoot, using Oscilloscope, everything goes on well, but still we can not synchronize in phase.

Since our design is based on FrameWorkLogic_r5, released on February,2009. I remember some update history mentioned in http://www.innovative-dsp.com/cgi-bin/dlWindowsBeta.cgi?product=X5-400M ,

there are probably updated version for synchronization, but I could not open the "update history" page anymore.

Is that possible that the un-synchronization is caused by FrameWork Logic?

[jherring]

What is the magnitude of the phase error you're recording?

The current logic release contains a design we tested specifically for phase issues compared to the external trigger. The attached app note discusses some subtleties of this issue, particularly with respect to cable length matching and delay trims that may need to be applied to the code to trim out cable delays.

Note that your external trigger edge must be synchronized to the sample rate, so you will need to use an external clock for this application in order to achieve good phase accuracy. There is no external access to the X5-400M onboard sample rate oscillator.

[jhenderson]

Update history mechanism has changed, but is again operational. See http://www.innovative-dsp.com/support/update.htm.

To my knowledge, we have not made any changes in the Framework that would affect synchronization between channels. How much skew between channels are you measuring? If your trigger signal is not disciplined into the sample clock domain, you will see a +/- 1 sample clock phase mismatch between acquisition cycles and between boards.

[AQAV]

Thanks for all the information.

We adjusted the trigger signal and sampling clock to make sure they are synchronized and disciplined, but these efforts still can not solve our problem.

The possible phase error is -1/+1 point, and changed from one measurement to another.

We made a same report to summarize the measurement result in the attachment.

[jhenderson]

Be when discipling the trigger signal, it should transition midway between the sample clock edge transitions.

It is certainly advisable to utilize the latest version of the BSP and Framework logic tools. Unfortunately, we cannot regress to support any older version of Matlab/Simulink or Xilinx ISE than that which is published on the beta site. So, it will be necessary for you to upgrade your tool chain.

[AQAV]

Can you give some information what was the upgrades you made from 1.11 to 1.12, related to "Fixed ADC external trigger phase alignment"? if that possible the situation I described can be solved after that modification?

We can update the tool chain, but it will generate a lot of work and consume many time for re-development of our own algorithm and softwares.

[AQAV]

This phase instability from one measurement to another already consumed us many days, and blocked our project progress.

Before upgrading the whole tool chain for new MATLAB BSP, we simply want to be sure that problem can be solved by doing so. If there is easier solution to fix the problem, we can then avoid many un-necessary additional efforts.

Thanks for understanding.

[Pat Carr]

[AQAV]

Thanks for your reply, Pat.

Following your suggestion, We have upgraded all our design to the latest MATLAB BSP in Xilinx 12.3;

Since We have four boards, two of them are version E, the other two are version F. The synchronization problem is solved for version E boards, but for the two version F boards, the phase relationship between two ADC channels is still NOT stable from one measurement to another, as described in the report I attached before.

I use the v7.4 RevE MATLAB BSP logic to generate the final bitstream file. Is there any difference between RevE and F in MATLAB BSP?

We use the same trigger and clock for all four cards. Any tips will be greatly appreciated.

[Pat Carr]

[AQAV]

[Pat Carr]

We're currently planning to reproduce the issue here, likely tomorrow.

Thanks for your feedback.

[AQAV]