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francis
Joined: 29 Oct 2007 Posts: 4 Location: Jordan
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Posted: Wed Oct 31, 2007 4:02 am Post subject: using snap example |
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hi,
I think I'm facing a problem when running snap example for data acquisition. I found that, when setting the source of ADC clock as PLL and choosing the crystal as its frequency reference, I can't extend the sampling frequency more than 43.3 MHz. So, how could I remove this limitation. Is there any parameter that I forgot to set?
best regards..
Francis |
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jhenderson Site Admin
Joined: 07 Mar 2006 Posts: 2254 Location: So. Cal. USA
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Posted: Wed Oct 31, 2007 8:27 am Post subject: Sample rate ceiling? |
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Please elaborate on the nature of the failure. What leads you to believe that you are unable to sample at rates beyond 43 MHz? Is disk data logging enabled? Which channels are enabled? Please post the BinView .bin/.bdd data files if they are available and relevant. _________________ phpbb1 |
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ahsantanvir
Joined: 09 Nov 2010 Posts: 9
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Posted: Mon Jan 03, 2011 6:45 am Post subject: |
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Hellow,
i had to develop a test scenario for varification of my configuration on GC5016 DDC , well here is test scenario:
i give sinoside signal at input and visualize the output, as i am using Innovative DR Board so i see output of GC5016 on scnap application, when i bypass cic and cfir filters i get exact downconverted signal from my nco and hencr no problem, but when i give input to ddc using cfir as low pass filter then i get cutoff at exact frequency but the issue is that the output is not the one as expected,
here is the case using nco at 10MHz(freq), lowpass filter with cutoff at 200KHz, Sampling frequency 39.6(Fck), cic decimation 20 , fir decimation 2
when input is 5MHz Output is 0 MHz (almost)
when input is 10.1 MHz the output is 4 MHz (this should be at .1MHz or 100 KHz)
when input is 10.2 MHz the output is 8 MHz (this should be at .2MHz or 200 KHz)
and above 200KHz There is no signal which is as expected
now please guide me what can be the issue and what is the main reason behind this unexpected output
regards Ahsan |
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ahsantanvir
Joined: 09 Nov 2010 Posts: 9
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Posted: Mon Jan 03, 2011 6:49 am Post subject: |
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Hellow,
thanks alot Radio-Joe for good suggestions, i had to develop a test scenario for varification of my configuration on GC5016 DDC , well here is test scenario:
i give sinoside signal at input and visualize the output, as i am using Innovative DR Board so i see output of GC5016 on scnap application, when i bypass cic and cfir filters i get exact downconverted signal from my nco and hencr no problem, but when i give input to ddc using cfir as low pass filter then i get cutoff at exact frequency but the issue is that the output is not the one as expected,
here is the case using nco at 10MHz(freq), lowpass filter with cutoff at 200KHz, Sampling frequency 39.6(Fck), cic decimation 20 , fir decimation 2
when input is 10MHz Output is 0 MHz (almost)
when input is 10.1 MHz the output is 4 MHz (this should be at .1MHz or 100 KHz)
when input is 10.2 MHz the output is 8 MHz (this should be at .2MHz or 200 KHz)
and above 200KHz There is no signal which is as expected
now please guide me what can be the issue and what is the main reason behind this unexpected output |
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