TX I/Os

[yasirjaved]

Hello,
I am using TX mounted on a Quadia board. I want to output a SYNC pulse aligned with start of data from DAC. It seems that if we use TX framework logic, the only option for I/Os is to use on of six user defined I/Os at XMC connector. So I tried using that. In the framework logic of Quadia board supplied with the boards, the user defined I/Os at XMC were not connected (Though PINs are mentioned in Framework logic user guide). I added the pins in UCF and top level file.
The problem I am facing is that User defined I/Os from TX are LVTTL signals. If we set user defined I/Os at Quadia to be LVTTL, it does not synthesize because there are other LVCMOS25 pins on the same bank. If I set these I/Os to LVCMOS25 and accordingly change the user defined I/Os in TX to LVCMOS25 then the TX framework logic does not synthesize because there are LVTTL I/Os in the same bank.
Some spare I/Os are also mentioned in Quadia description on PMC J2, but there is no mention of FPGA pins connected to PMC J2 in TX section of Framework logic user guide nor could I find them in the supplied VHDL top level.
So I am a bit stuck up in simply generating an output from TX card mounted on Quadia.
Your help is appreciated, if you can guide me in both these things
1- How to get a few I/Os from TX mounted on Quadia?
2- Where to start the change in Framework logic with if I want o generated a SYNC pulse aligned with data?
Regards,
Yasir

[jherring]

To generate a signal from the PCM-TX to the Quadia logic, you can use the JN4 digital I/O signals. These are PMC-TX U1 I/Os pinned out to the JN4 connector, which in turn connects to U14/U15 on the Quadia. The PMC-TX provides 32 data pins plus a handful of control pins, but these do not line up one-for-one with the data pins on the Quadia JN4 pinout, so use care in selecting a pin for your signal. For example, J4_IO0 on pin R1 of the PMC-TX logic connects to pin 34 on JN4, which in turn connects to PMC_IO33 (pin AA5) on U14/U15 on the Quadia. Both the Quadia and PMC-TX logic pins in this case are on 2.5V banks, so you can use the LVCMOS25 IOSTANDARD on the two logic designs.

The SW_TRIGN signal in the PMC-TX logic is the software trigger that enables reads of the data FIFO to drive signal data to the D/As. Pinning this signal out as your sync signal would give an edge close the to beginning of D/A output, less transport delay through the D/A and output amps.

[yasirjaved]

I could not understand the connections because I could not find AA5 pin in Quadia's UCF. The Quadia board that I am using is Rev H (printed on it), Is it some version mismatch? Aren't j4_data pins in Quadia and TX connected one to one?

[yasirjaved]

Hello,
I mistakenly misquoted about AA5 in my previous post. Here is the scenario again:

Actually I am a bit confused due to this part of your previous post:
"J4_IO0 on pin R1 of the PMC-TX logic connects to pin 34 on JN4, which in turn connects to PMC_IO33 (pin AA5) on U14/U15 on the Quadia."

In Quadia's UCF file that I have been provided, FPGA's AA5 pin is connected to j4_link_data<3>.

My initial assumption was that the bus j4_link_data(31 downto 0) in Quadia's top-level is connected one-to-one with j4_link_d(31 downto 0) in TX's top level. Is this assumption correct?

Since I did not require J4 interface so I removed J4 master from Quadia and Slave from TX. Now I am trying to connect j4_link_d(3 downto 0) in TX's top level with some SYNC signals. I assume that I will receive these SYNCs at j4_link_data(3 downto 0) in Quadia's top level. I want these SYNCs out at J5 connector. So in Quadia's top level I am connecting j4_link_data(3 downto 0) to tp(9 downto 6). Based on these changes I expect to get the SYNCs at J5's pin number B21, A21, D21 and E21 (If TX is connected to Quadia's FGPA0).

Are these connections correct? From your previous post it seems I might be missing something..

[jherring]

For the complete connection between the PMC-TX and Quadia via the JN4 connector, you'll need to refer to several tables in the Framework Logic User Guide (available on the II website under the Documentation Downloads for the PMC-TX):

1) For the PMC-TX JN4 connector and logic pinout, see Table 118 in the Framework Logic User Guide (starts on page 262). Note that there is one error in the table: the Clock signal is listed as being on pin E18 of the FPGA, but it's actually on pin K19.
2) For the Quadia JN4 connector and logic pinout, see Table 142 in the same document (starts on page 309). For purposes of communication between the PMC-TX and the Quadia over JN4, you can ignore the rows of the table which refer to JN1 and JN2 pins.

These two tables will give you the pinouts for the two logic devices and the connections through the JN4 connector. As I noted in my post above, the signal names in the table do not match across the two boards because we used a different functional pinout on the PMC-TX versus the Quadia, but there are quite a few signals in common and it's easy enough to construct a small bus to allow communication.

You mention in your last post that you need four signals: these could be placed on JN4 pins 6, 8, 9, and 12 as these pins all have connections available on both boards. These signals would be on pins T3, U3, M2, and N2, respectively, on the PMC-TX logic, and on pins AF3, AE2, AE1, and AE4, respectively, on the Quadia logic. You mentioned that you already removed the existing JN4 logic interfaces from the two boards' VHDL files, so all you should need to do is connect your desired signals to these four pins on both designs.