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kberndsen
Joined: 20 Jan 2012
Posts: 57
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 Posted: Wed Mar 14, 2012 1:15 pm Post subject: Write dual-port RAM contents via Wishbone I/F |
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Do you have any examples of writing the contents of a block RAM from a Wishbone write sequence. I'm using this block RAM for a LUT, but it could also be for a pattern generator or dynamic filter coefficients.
I'm creating my FPGA image for the X6-1000 by modifying one of the Matlab BSP examples with Simulink/System Generator.
So I'd like to know if anyone has implemented this process and could share the model.
SYSTEM: 64-bit Windows 7, ISE 13.2, Matlab 2011b |
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smoses
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Joined: 08 Jan 2009
Posts: 121
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| Posted: Fri Apr 06, 2012 9:37 am Post subject: |
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To write to a block RAM, you need 3 signals:
1- write strobe
2- write address
3- write data
These signals can be driven from a wishbone slave. A similar code can be found in ii_afe_intf_regs.vhd (pll_spi_*) signals. |
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kberndsen
Joined: 20 Jan 2012
Posts: 57
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| Posted: Tue Apr 17, 2012 11:10 am Post subject: |
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| Is it possible to do this in the user space in System Generator? Has anyone ever tried anything like that? |
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smoses
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Joined: 08 Jan 2009
Posts: 121
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| Posted: Tue Apr 17, 2012 12:35 pm Post subject: |
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| The registers can be placed in any address space. I don't know if anyone has ever tried it though. |
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nicolasroch
Joined: 23 Jan 2012
Posts: 26
Location: France
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| Posted: Tue Jul 17, 2012 11:31 pm Post subject: |
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Hi kberndsen,
I would also be interested in having such a tunable LUT (for a tunable IQ demod). Did you finally implement this with System Generator or did you use VHDL as recommended by smoses?
It would be nice to have feedback on your experience. I will try to implement this with SysGen anyway....
Nico |
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