Default Example.

[khaty]

Was going through the step of the Default Example in "X3-Servo Matlab BSP Manual.pdf" document and while the system generator part worked fine and I ended up with h/w co sim library and all the necessary generated files that are needed for VHDL I could not proceed further. I have an eInstrument system which has x3-servo integrated into it so don't have a JTAG connection. I therefore failed to go through the steps that follow double clicking the h/w co sim block (i.e. free running vs single stepped, and the cable type, etc..).
The questions I have are:

Do I still need a JTAG link despite me having the complete eInstrument system with the x3-servo integrated?

How do I go about programming my x3-servo (through using snap.exe or wave.exe)? Tried just copying the *.bit file that was generate into the eInstrument platform (which has x3-servo) and tried to configure the hardware, but it failed to do so. It was not quite clear why that is in the document.

I was then directed to pages 52/53 of "X3-Servo Matlab BSP Manual.pdf " and tried to go through the steps there and still got an FPGA failure to configure correctly message.

I am using Xilinx ISE and Xilinx System Generator version 13.4 (for both).
I am using Matlab 2010b (since system generator did not work for Matlab 2012a).

[ravithakur]

Please use the following pdf file for the supported tool versions

http://www.innovative-dsp.com/support/datasheets/FPGADevSWReq.pdf

You will need a jtag pod to program the card with the hardware cosim bit file. If you generate the bit file using the ise project, you can use either of the exe files to program the card.

One thing you can try is using the VsProm.exe in C:\Innovative\X5-400M\Applets\VsProm to program the card with the hardware cosim bit file.

[khaty]

Do I need a jtag even though I have the complete eInstrument with integrated x3-servo system?
I thought the whole point of the integrated system is the removal of the need for a jtag.

[ravithakur]

For hardware co-simulation, the tool requires that you program the FPGA via a jtag cable. Using either snap.exe or wave.exe to program the board will give a FPGA load failure error. You will see the same error if you use the logicload.exe
in *\X3-Servo\Applets\LogicLoad\Vc9\Release.

I would recommend that you generate the standalone bit file using the ISE project. The bit file generated can be programmed using all of the above mentioned methods.

[khaty]

I tried to follow the step which generate the standalone bit file to upload to the FPGA via snap.exe but I as a new-bee to all these Xilinx tools, I must have done some wrong as it failed to build in the Xilinx ISE. Could you so kindly list the process of generating the standalone bit with Xilinx ISE having more comments for each point. A bit more detail than what exist in the "X3-Servo Matlab BSP Manual.pdf"

Many thanks.

[ravithakur]

To generate the standalone bit file, use the x3_servo_implement.mdl.

1. When you open the system generator token in the model file, make sure the compilation is set to NGC Netlist. Do so if it is not. Under settings, deselect "include clock wrapper" option

2. The part should be Spartan-3A DSP xc3sd1800a-4fg676, select the part if it is not. Make sure the target directory is ./ngc_netlist and click on generate. (make sure you have Ts=1.125e-8 in the workspace, if you dont, type in "Ts=1.125e-8" in the command window without quotes to add it to the workspace before clicking on generate)

3. After the compilation ends copy x3_servo_implement.ngc from ngc_nertlist folder to the *\Matlab\Logic folder

4. Open the ISE project and double click on the vhd file x3_servo on the hierarchy pane. make sure the generic "implementation_logic" is set to '1' and generate the bit file.

If you are still seeing errors, please attach the error messages and I will assist you in debugging them.

[khaty]

Thank you that worked.
When I programmed the FPGA with the standalone bit stream that was generated (having following your suggestion), the upload/programming was successful (usning snap.exe and stream.exe). I was hoping to override the initial setup such that what ever I put at my input (in terms of analog signal) is piped to the output (through the DAC) and I can see something on the scope.
Neither program provided with that ability. Do I have to go in and start building new C executable to perform a talkthrough test (i.e. analog->ADC->(could be any signal processing but for simplicity is a pass through)->DAC-output)? or Do I have to modify the simulink module and generate the lot again? Do you have any documentation the explains how to do this simple talk-through test?

[ravithakur]

In the implement example you can try connecting the adc 0 input block to the dac 0 output block with some buffering between them to achieve what you need. After the model is built, follow the process to generate the stand alone bit file and program the card. You will need to use the stream software in order to run the adcs and dacs together.