Joined: 07 Mar 2006
Location: So. Cal. USA
|Posted: Thu May 01, 2008 8:09 am Post subject: X3-10M limitations
|I want to clarify some limitations of the 10M, so that one can make informed decisions in the use of this product.
Bus Rate Limitation
Innovative's X-3 series modules employ a single PCI Express lane for communications with the host. Consequently, the maximum sustained data rate between the module and Host memory is 200 MB/s. However, the 10M is capable of sampling each of it's eight analog inputs at rates up to 25 MSPS, resulting in a data flow of up to 400 MB/s. Clearly, the bus interface is insufficient for sustained, full-rate data flow.
In most applications involving the 10M, the FPGA is used to capture the data at the full 25 MSPS rate from all channels, but the data rate to the Host is reduced either via triggering or a custom algorithm in the FPGA. For instance, in one recent application, the 10M used framed-mode triggering to acquire data at full speed. The trigger duty cycle was about 40%. Consequently, the data rate to the PC is under 200 MB/s.
Analog Bandwidth Limitation
The 10M A/Ds are capable of sampling at rates to 25 MSPS. However, the differential input amplifiers used on the design are band-limited to about 7 MHz. That is, the -3dB point in the frequency response of the input front-end is less than the Nyquist sample rate of 12.5 MHz if the 10M is sampling at full rate.