Posted: Tue Mar 02, 2010 10:20 pm Post subject: how to change sys_clk in x5-400m h/w
how to change sys_clk from 200MHz to lower clock in h/w ?
my DSP design can not run at 200MHz clock, when i generate my project, i meet time constraint promble!
how to recompile "core\x5_400M_top.ngc", this ngc set the sys_clk to 125MHz*1.6 = 200MHz,
Joined: 17 Apr 2006 Posts: 118 Location: Simi Valley
Posted: Thu Mar 04, 2010 10:28 am Post subject:
Hi,
First run the timing analyzer and pin point the nature and source of error.
SX95T FPGA clock is set at an optimal rate to meet timing for most of the carefully planned designs.
Amit Mane
Design Engineer
Innovative Integration Inc.
Simi Valley,Ca
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