CHIRP GENERATION

[anehila]

HI,
I'm trying to generate a chirp signal with four DDS and phase offset.
When I visualize I and Q signals at the scope at the output of DAC0 and DAC1, signals are not SINEWAVE, there is a time shift between to successive pulses.

Therefore, I tried generation of simple pulses and ramp pulses, I have the same problem
* synchronization problem
* Amplitude problem: the ramp is not linear.
How can you do to synchronize ouputs of DAC. and generate perfect chirp pulses
thinks

[ckang]

There are a few ways to generate a ramp using T5-TX: FPGA mode and Software pattern mode, I am not sure which mode you are using. If you enable the pattern mode, you have to go to the pattern page and click 'execute the pattern' to generate the correct wave. Otherwise, if you click run in the steam page, you will get a non linear ramp.

So, first, let's make sure the settings are correct.

1. what mode are you using to generate the ramp and chirp, FPGA mode, Pattern mode, or Chirp mode? or are you generating the chirp and ramp using your own tool.

2. what's your configuration in each page?

---> setup page: what is the sample frequency? In waveform source, is FPGA enabled or disabled? What are the sources selected for both FPGA and software?

---> chirp page: what is your settings in the page?

---> please describe the steps you do when you generate and play your wave.

[anehila]

Thank you Ckang for your reply;

I'm trying to generate ramp and chirp signals using my one vhdl code.
I instantiate my code at two levels:
1- In test generator module
2- At DAC top level module
My vhdl modules based on XILINX DDS v2.1 are using SYS_CLK and srst.

My objectives are to generate a chirp (I&Q signals) at 1GSPS, and frequency varies between 0 and 500MHz. Pulse width between 250 ns and 1us, and Pulse Repetition time between 1us and 10ms.

Thus I instantiate my CHIRP_GEN between DAC_TOP and DEINTEARLEAVER, and I use VFIFO to acquire pulses description.
The output of chirp generator then is connected like that at the input of DAC_TOP level
dac0_din receive cosine(63 downto 0)
dac1_din receive sine(63 downto 0)

I have an other question
Why you have used Cordic algorithm instead of xilinx DDS to generate sinus?
thanks for you

[Pat Carr]

Bonjour anehila,

Have you tried simulating the entire design after you added your logic?

In which mode are you running, stream or pattern mode? Stream mode requires the host to send data continuously, thus failing to acquire data fast enough to drive the DACs at 1GSPS. Pattern mode fills the vfifo memory with a wave pattern, and then plays it continuously meeting the required DAC input stream.

I see your chirp_gen uses 'CE' as its input enable. What signal is driving this input at the top level?

I'd strongly recommend simulating the design before trying it on hardware.

[ARNAUD]

Dear Support,

The customer would like to have information about DDS of ii_dac_test_gen.vhdl module. Indeed, they are inaccessible (Innovative IP (netlist))
He wants to know how use the signals “phase_inc_wr (input)” and “valid (output)” and their relationship (when “valid” signal is active compared to “phase_inc_wr” for example)
He wants to use these DDS to generate pulses radar.

[Pat Carr]

The input phase_inc_wr is used to load the initial phase increment and phase offset. Once loaded, the dds_en input is used to generate the output wave. Whenever valid is asserted, sine and cosine outputs are valid outputs. Keep in mind that from dds_en to the valid assertion, there could be 2 or 3 latency cycles.

From the component documentation:

This component generates 16-bit sine and cosine waves.
The output phase is controlled by the phase offset and the
output frequency is controlled by the phase increment.

phase increment = Fout * 2^(accumulator width) / Fclk,
where accumulator width = 24, Fclk = clk frequency = 250e6 Hz.

[ARNAUD]

The customer would like to have details about phase_inc_wr.
When “phase_inc_wr” must be set at 1?


You said that “ dds_en to the valid assertion, there could be 2 or 3 latency cycles”. Is it on rising edge or falling edge of phase_inc_wr

Can you send a chronogram on the operating prinicipe of ii_dac_test_gen?

[Pat Carr]

[ARNAUD]

Dear Support,

The customer encounters difficulties to use the DDS of ii_dac_test_gen.vhdl module.
He would like to know how it works.
He requests a chronogram with timing of DDS, for:
- Phase_in
- Phase_in_wr
- Dds_en
- Valid
He needs the relation between all the variables.

Could you please send me the maximum of information to help him?

[ARNAUD]

You can find enclosed chronogram.

Could you please confirm the DDS working and complete ?? in this pdf file?

Can we repeat the attached chronogram to the update the DDS to do CHIRP generator?

[Pat Carr]

Bonjour Arnaud,

I'll describe the question marks in the diagram from left to right.

a) The setup time for phase_inc can be as low as 0 clock cycles.
b) The pulse width of phase_inc_wr must be at least 1 clock cycle.
c) The setup of dds_en can be as small as 1 clock cycle.
d) The latency of valid output from dds_en is 3 clock cycles IIRC. This can be simply obtained by running a simulation, which is highly recommended.

[ARNAUD]

Syst_clk is used by a lot of modules in the Logic framework at 300MHz; can we decrease syst_clk frequency at 260MHz (without changing anything else) with logic framework always functional?

Could tell us if it is difficult to implement a CHIRP generator?
What is development time to do this?

[Pat Carr]