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samehalkady
Joined: 20 May 2010 Posts: 9
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Posted: Mon Feb 14, 2011 5:20 pm Post subject: X5-400M Matlab/Simulink Programming for signal processing |
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Hello support;
I am trying to program the FPGA on a X5-400M card using Matlab/Simulink. My goal is to add a FFT routine in the path of data streaming, so that instead of streaming-out time domain signal, I would stream-out the power spectrum of the signal. I started with the default example located in X5-400M_r7.7. I added a 32-to-16 fifo right after ADC_0_INTF, followed by a FFT7.1 block followed by slice, and reinterpret blocks, then a complex multipler M-block that I generated followed by slice and reinterpret blocks. then a 16-to-32 fifo, which feeds the II_Interleaver. I compiled the design, and generated a hwcosim lib block, then used the jtag cable to run the hwcosim. I keep getting 0's as output of Ch0 (using a function generator at Ch0 input, running snap, and viewing the signal with binview) . I do not know what goes wrong. The FFT routine works fine when I simulate it separately in Matlab/simulink. I attached a copy of the mdl file along with the matlab function of the M-code I added.
I appreciate your help.
Thanks. _________________ Sameh Abdelazim |
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bkao
Joined: 09 Feb 2007 Posts: 200 Location: Innovative Integration
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Posted: Mon Feb 14, 2011 5:38 pm Post subject: |
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Please attach the files.
Billy |
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samehalkady
Joined: 20 May 2010 Posts: 9
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Posted: Mon Feb 14, 2011 8:41 pm Post subject: Re: X5-400M Matlab/Simulink Programming for signal processi |
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| samehalkady wrote: | Hello support;
I am trying to program the FPGA on a X5-400M card using Matlab/Simulink. My goal is to add a FFT routine in the path of data streaming, so that instead of streaming-out time domain signal, I would stream-out the power spectrum of the signal. I started with the default example located in X5-400M_r7.7. I added a 32-to-16 fifo right after ADC_0_INTF, followed by a FFT7.1 block followed by slice, and reinterpret blocks, then a complex multipler M-block that I generated followed by slice and reinterpret blocks. then a 16-to-32 fifo, which feeds the II_Interleaver. I compiled the design, and generated a hwcosim lib block, then used the jtag cable to run the hwcosim. I keep getting 0's as output of Ch0 (using a function generator at Ch0 input, running snap, and viewing the signal with binview) . I do not know what goes wrong. The FFT routine works fine when I simulate it separately in Matlab/simulink. I attached a copy of the mdl file along with the matlab function of the M-code I added.
I appreciate your help.
Thanks. |
_________________ Sameh Abdelazim |
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bkao
Joined: 09 Feb 2007 Posts: 200 Location: Innovative Integration
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Posted: Tue Feb 15, 2011 10:33 am Post subject: |
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Sameh,
I suggest you provide proper flow control along the path.
1. Even you set V5_FIFO_32i_16o rd '1', you can't drain the data fast enough out of the FIFO. So this FIFO will be overflow immediately.
2. I can't figure out what the FFT output is when input is corrupt.
You shall carry valid signal with the data for all signal processing components. The processing chain needs to be changed because it can't handle the data rate.
Billy |
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