Create a bitstream stand alone with BSP.

ARNAUD

Dear Support

A customer has a problem to create bit stream stand alone with BSP.

Software release:
BSP version 7.3
Version xilinx : 11.3
Version MatLab : R2008b

He followed the procedure at the end of BSP manual and removed gateway:
“Remove all the memory mapped gateway from the design as shown in the x5_400m_implement.mdl file in the default example folder”

Case 1: NGC netlist without Gateways, error during generation (see attached files called “erreur1.JPG” & “sysgen1.JPG”)
Case 2: NGC netlist with Gateways, compiling error with ISE (see attached files called “erreur2.JPG” & “sysgen2.JPG”)
Case 3: Bitstream, error during generation (see attached files called “erreur3.JPG” & “sysgen3.JPG”)

bkao · Posted: Tue Mar 22, 2011 1:53 pm Post subject:

Arnaud,

Can you attach the mdl project?

Billy

bkao · Posted: Tue Mar 22, 2011 3:10 pm Post subject:

For case 1 and 2, it seems the user doesn't replace the gateways with constants. So the compiler complains no proper inputs.

For case 3, you can't select bitstream in Xilinx token. You need to generate the ngc netlist and compile with the FrameWork logic in ISE for the final bit file.

Billy

ARNAUD · Posted: Wed Mar 23, 2011 6:11 am Post subject:

Hello Billy,

The customer has repalced gateways with constants.
You can find enclosed .mdl file.

bkao · Posted: Thu Mar 24, 2011 2:54 pm Post subject:

Arnaud,

Please attach the file.

Billy

ARNAUD · Posted: Thu Mar 24, 2011 11:48 pm Post subject:

Enclosed .mdl file

amane · Joined: 17 Apr 2006 Posts: 118 Location: Simi Valley

Hi Arnaud,
I have attached a Matlab BSP manual for your reference.
Page 71 and 72 describes the procedure for standalone bit image generation.

Sincerely,
Amit Mane
Innovative Integration Inc
Simi Valley Ca 93065

ARNAUD · Posted: Tue Apr 05, 2011 1:44 am Post subject:

Hi Amit,

With the standard x5_400m_implement.mdl, there is no problem to create bit stream standalone.

The problem is with their .mdl file.

If you have a clue ...

amane · Joined: 17 Apr 2006 Posts: 118 Location: Simi Valley

Hi Arnaud,
Please try to compile this file FOR STANDALONE BIT IMAGE.
Sincerely,
AMIT

ARNAUD · Posted: Wed May 11, 2011 5:24 am Post subject:

Dear support,

A customer tried to generate a .bit stream standalone but he has several errors messages. Use attached file called "error_message".

You can find enclosed .ngc file generated by Simulink and project files.

Tools used:
ISE 11.3 & System generator
MatLab 2008b

Thanks for your help

amane · Joined: 17 Apr 2006 Posts: 118 Location: Simi Valley

Hi,
It looks like the ngc was generated with memory mapped gateways from Xilinx System Generator.
Before the compilation you must remove all the user defined input and output gateways from the design.
Sincerely,
Amit

ARNAUD · Posted: Fri May 13, 2011 12:36 am Post subject:

Hi Amit,

Indeed, there is one gateway. The customer cannot remove this gateway because he is using a dual RAM port which he is using only input A for write.
If he does not put a gateway on dinB, there is an error message which mentions that the compiler cannot resolve this type of data:
Rates and types converged for the feedback path through these blocks.However, the solution contains unknowns. Could not establish types for the blocks listed at the end of this message.
He cannot use Assert bloc because it requires data input.

Can tell us the way to solve this issue?

ARNAUD · Posted: Fri May 13, 2011 6:56 am Post subject:

Hi Amit,

I don’t if you can help on this issue
You can find below the request:
“We have tried to test our system in co-simulation. We have noticed that the scroll bar time under Simulink did not correspond to the real time. We believe that this can cause problems if we work in continuous flow. Can you confirm?
To bypass these issues, instead of use ADC to snap data (X5-400M), we wrote data in hard using ROMs. However, our system does not work. When we are using Snap example, HsData.bin includes only hexadecimal string "0280 0000 0100 0000" repeated 350 times instead of the result expected.
When we are doing a simulation of our model, it works as expected.
Do you a clue to explain that it does not work in co-simulation?"

Thanks

ARNAUD · Posted: Wed May 25, 2011 8:17 am Post subject:

Dear Support,

To bypass this problem, the customer add a constant on the input B of the dual RAM port.
The design works as expected.

However, the customer would like to know if there is a way to not put a constant of second port of dual RAM Port?

Attached design

jpat34721 · Joined: 30 Nov 2010 Posts: 64 Location: Santa Rosa, CA

item 10 on page 72 of the x5 manual you quoted says "Open the ISE project at <X5 Root>/400M/400M/Matlab/rev_E/Logic"

The corresponding directory is not there for the X6 and the only *.xise file I can find (x6_400M.xise) is under x6_400M/Hardware/FrameWorkLogic/X6_400M_r1.0/400M/logic/rev_a/ise.

Is that the one I should use?

Thanks,
Jeff Patterson
Agilent Technologies