Coherent Pattern Generation

yasirjaved · Joined: 23 Sep 2010 Posts: 8 Location: Pakistan

Hello,
I am using PMC-TX as a waveform generator. I want four aligned patterns to be played simultaneously on each DAC. I am using pattern generation mode to do that. The size of waveform is such that one Ping buffer is sufficient to generate it. I have been able to generate the waveform by modifying the testbed software supplied with TX but the issue I am facing is that TX's DACs operate in pairs. The DACs in one pair seem to operate aligned to each other but there is an offset between both pairs. The offset seems to change every time I send the pattern. Is there any way that four patterns be played aligned with each other on each DAC?

Regards,
Yasir

jhenderson · Posted: Thu Sep 23, 2010 2:17 pm Post subject: X5-TX channel alignment

This problem stems from defects in the D/A silicon. We have developed a workaround, but it requires a rev C or later X5-TX PCB and firmware release 2.2, posted on the beta site this week.

Unfortunately, there is no way to retrofit older revision boards to eliminate this problem. However, we are willing to exchange older stock with rev C boards at a cost of 1/4 current domestic price. Contact sales to arrange the swap.

yasirjaved · Joined: 23 Sep 2010 Posts: 8 Location: Pakistan

Hello!
If the issue is in silicon then there should be offset between the two DACs in one pair, but the DACs in one pair seem to be aligned to each other.
My initial guess was that the offset is because of two separate signal paths in the framework logic for the each pair of DACs. But your post suggests that my guess is wrong and there is no way around. Is it so?
Regards,
Yasir

jhenderson · Posted: Mon Sep 27, 2010 9:24 am Post subject:

The nature of the silicon defect is that the two channels on a given D/A device are always in sync, but the phase of signals from one D/A device is not the same as a second D/A device, even if fed the same clock and trigger.

This problem has been confirmed by the device manufacturer. As a work-around for this, the latest rev of the PCB includes a high-speed comparator and other circuitry which allows the FPGA to monitor the absolute phase of the four output channels from two D/A devices. As data flow commences, the FPGA automatically performs a training cycle which "learns" the phase error for each device pair and injects a delay to match the timing from both D/A devices.

As a consequence, all channels on each card and even channels on multiple cards are all synchronized with one-another. If provided a common clock and a suitable high-speed trigger marshaled into the sample clock domain, all channels on all boards start and remain in phase throughout a run.