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jhenderson
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Joined: 07 Mar 2006
Posts: 2254
Location: So. Cal. USA
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 Posted: Fri Jul 29, 2011 7:43 am Post subject: Aperiodic external clock |
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| Quote: | For a data acquisition system involving a swept source laser for an optical coherence tomography application we are currently looking for a data acquisition board that can handle a non-continuous external clock.
Therefore, I was wondering if the X6-400M board from Innovated Integration can handle such a feature.
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Attached is the data sheet for the ADS5474 ADC, which is used on the 400M design. Page 7 of the datasheet details the clock requirements. There is no stated maximum for the clock pulse duration, which leads me to believe that the device can operate with an aperiodic clock. However, the data sheet indicates that all of the specified performance figures were gathered using a clock with 50% duty cycle and the device may exhibit some performance degradation if the clock rate is varied.
You may capitalize on our return policy which allows the customer to return the card within 30 days without any restocking penalty if it does not meet their requirements. This would allow the customer to inject their test signals in-situ to characterize the board's performance with live signals.
| Quote: | We are still concerned with some issues with the external triggering requirements for both boards.
According to the data sheets and user manuals, the X5-400M requires a LVTTL signal as an external trigger. The trigger that we have has a high level of 1.6V. Since LVTTL requires a minimum high level of 2.0V, we would need to amplify (or offset) our triggering signal. On the other hand, the X6-400M does not seem to have the LVTTL requirement for the external trigger, but it requires an external trigger with a minimum frequency of 1 MHz and a maximum amplitude of 1.5V. Our trigger signal is 35 kHz and a max amplitude of 1.6V. Thus, this would not work either.
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The X6-400M trigger is AC-coupled, but two ways to handle the 35Khz.
1. Sample the trigger with the A/D clock and detect rising or falling edges. So long as the trigger has an edge with slope <10 ns/V, the trigger input to the FPGA will see this edge as a pulse. This pulse can be then sampled by the FPGA and detected.
2. The trigger input can be reconfigured to be DC input. The input signal would need to meet these requirements:
This is a differential input to a buffer IC (TI CDCLV1204) The negative input on the X6-400M is tied to 1.25V, so the trigger input is required to be 1.25V +/-0.3V min, 1.25V+/-1.6V max. Minimum absolute voltage must be > -0.3V, maximum absolute voltage < 2.8V. Input is 50 ohm terminated. |
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jhenderson
Site Admin
Joined: 07 Mar 2006
Posts: 2254
Location: So. Cal. USA
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| Posted: Mon Aug 01, 2011 1:04 pm Post subject: |
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| Quote: | Thank you for the quick reply. I have some questions though:
1. Sample the trigger with the A/D clock and detect rising or falling edges. So long as the trigger has an edge with slope <10 ns/V, the trigger input to the FPGA will see this edge as a pulse. This pulse can be then sampled by the FPGA and detected.
Would the input port for the external trigger signal then be the external trigger port or one of the analogue input ports? In either case, would it still be possible to sample the (other) analogue input with an external clock signal?
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The input would be the external trigger input. When I say "sample", I mean to say that the FPGA samples the external trigger input on each sample clock edge. |
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