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gilles_houzet
Joined: 12 Jul 2011
Posts: 33
Location: switzerland
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 Posted: Wed Jan 09, 2013 7:17 am Post subject: VPX6-COP framework logic data flow |
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- What kind of data is between VFIFO data buffer and VITA router, is it raw data which are comming from/to the PCIe interface ?
- can I replace the VITA router with a custom VHDL bloc feeded with raw data coming from the VFIFO with handshake (or generating data to the VFIFO) ?
- Is the VFIFO working like in the x3-dio board ?
THANK YOU FOR YOUR ANSWER
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alphabravocharliedeltaecho |
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smoses
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Joined: 08 Jan 2009
Posts: 126
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| Posted: Thu Jan 10, 2013 9:31 am Post subject: |
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The diagram is incorrect. In the VPX-COP framework logic, there are no VITA aware (such as VITA router) components. So raw data flow throughout the logic except to the PCIe interface. Velocia format packets flow between the PCIe interface and the packetizer and deframer. The VFIFO works just like a normal FIFO with the exception that the input should be an even number of 128-bit words.
Shant |
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