Latency

[jhenderson]

We measured the ADC and DAC latency in the X6-1000M and the
results are as below:

1) For the X6-1000M ADC @1GSPS: from the analog input to the ADC
interface Physical layer.
- From the ADC analog input to the digital output/FPGA pins : 7 fs clock
cycles.
- From the FPGA pins to the PHY layer (where 4 samples are provided in
parallel at fs/4 rate) : 33 fs clock cycles
So the total delay is 40 fs clock samples.


2) For the DAC @1GSPS : from the DAC interface Physical
layer to the analog output.
- From the PHY layer (where 4 samples are provided in parallel at fs/4
rate) to the FPGA pins : 10 fs clock cycles
- From the FPGA/DAC pins to the analog output : 84 fs clock cycles.
So the total delay is 94 fs clock samples.