External reference issues (?)

[dohertk]

We're operating with our X6-400M being just one component of an extended, phase coherent system; as such, we want the digitizer phase locked to a common external reference.

We seem to be having some difficulties in that regard. The internal oscillator reports phase lock, but measurements of the phase of the ADC sample clock vs. time show that it wanders quite a lot (nanoseconds) compared to the reference input.

We performed our measurements by generating a +3 dBm 100 MHz sinewave from an HP synthesizer, then splitting it; one copy went into the reference input, and the other into the ADC0 input. We specified a 100 MHz external reference (and verified that the software indicated reference lock) and a 100 MHz sample rate, then sampled several seconds worth of data and plotted the output (ref: attachments).

The input reference should have been divided down to some (unknown) comparison frequency, then multiplied back up to 100 MHz and used to sample the 100 MHz ADC input. If everything is perfectly locked we would sample the input sinusoid at the same point on every cycle, and we would get a constant value out.

What we get is only 'constant-ish'; reference the second of the attached plots for details. The point at which the input sinusoid is sampled varies by hundreds of LSBs; given the dV/dT of the 100 MHz input this is on the order of a nanosecond of drift.

To verify that it was the internal PLL having difficulties we changed our software to use the external 100 MHz as the sample clock (bypassing the PLL). We still saw considerable variation (ref: the first attachment), but it was on the order of 10's of LSBs instead of hundreds.

Do you have any suggestions as to what might be going on?

Kevin Doherty

[dohertk]

When posting, the first and second plots seem to have been swapped. The plot showing hundreds of LSBs is the external reference plot; that showing ~30 LSBs is the external clock plot.

K

[jhenderson]

Try increasing the level of the input reference clock. Use of just 3 dBm ~= .315V, is barely enough drive for the PLL input circuit. The data sheet indicates that inputs from .1 to 3.3V are permissible, but cautions that performance improves at higher input levels.

In general, use of a sine signal as a reference clock results in deteriorated jitter performance compared to a square wave, resulting from the low edge rates. Conversely, square wave inputs result in lower phase noise but more feedthrough.

Under the proper circumstances, the X6-400M PLL is capable of phase noise performance in the 300-600 fS range. Indirect proof of this can be obtained by digitizing a filtered input signal using the onboard PLL reference and analyzing the ENOB performance via BinView. When qualifying the board, we routinely achieved ENOB of 10.1-10.9, indicative of phase noise in the range referenced above.

[dohertk]

Your documentation calls out a max input value of -0.8 dBm on the reference input, though it also states that this equals 2 Vpp. (This is on pages 119/120 of your X6-400M user manual).

We noted the discrepancy, but were reluctant to (potentially) exceed the max input value by a factor of 10.

I'll try the higher amplitude and let you know how it works out.

K