X6-400M memory questions

irad002 · Joined: 09 Apr 2012 Posts: 2

I have a few questions about memory in X6-400M.

Is there any way to create multiple logical FIFO queues that use the same DRAM bank?The VFIFO component seems to provide only a single FIFO per physical DRAM bank. Also, is random access when reading/writing supported i.e. accessing a particular memory location by providing the address?

In the default logic configuration the VFIFO components are only used for buffering
data in front of the packetizer, deframer, router etc. What are the actual buffering requirements?Each VFIFO component provides up to 1GB of buffering capacity, which seems quite a lot just for real-time streaming of data to the host. Would it be possible to use the on-chip FPGA memory for packet buffering and release the external DRAM for computation?

In the Matlab BSP package, there are no blocks for accessing the DRAM memory.
It also appears that the flash memory cannot be accessed, which would be useful
if a MicroBlaze softcore processor was instantiated in System Genearator.
Is there any easy way around these limitations?

jhenderson · Posted: Mon Apr 30, 2012 5:12 am Post subject:

irad002 · Joined: 09 Apr 2012 Posts: 2

"In order to use the memory otherwise, you must author your own memory controller"

When one of the ADC or DAC channels is not used and a DRAM bank becomes available, are there any issues with using a VFIFO component to buffer data during computation, apart from having to pack 16-bit samples into 128-bit words? An important assumption in this case is that the system clock runs at 400 MHz to support the fastest ADC sampling rate.

Also, is a DRAM device model included in the VHDL testbench so that VFIFO can be simulated?

smoses · Distributor Joined: 08 Jan 2009 Posts: 121

In the X6-400M framework logic, the 4th LPDDR2 memory controller is not used to stream ADC or DAC data. It can be used for any purpose.

The interface to this VFIFO runs at the system clock rate and because of the burst length access type, even number of 128-bit words have to be written into this VFIFO in order to make it through the memory controller.

A VFIFO bus functional model is provided for simulation.