problem with pmc_dr project synthesize in xilinx 8.2

[amad]

we have successfully tested the DR board with one of the provided logic image (file name is pmc_dr.exo). data is received back n stored n ploted by the provided software application 'snap'.

documentation says that framework logic application contains all the basic implementation of the components on that board n cud be used to add aditional functioanlity according to the requirements.

WE have synthesized the provided xilinx pmc_dr projects in Xilinx 8.2. while genarating an exo file using IMpact we checked "automatically select PROM device" on the 3rd page (select PROM device) of the wizard. but no data stream is read by the snap app when this exo is downloaded on the DR board's fpga. we tried to generate exo files using bit files named 'pmc_dr.bit', 'pmc_dr_routed.bit' (available in the PMC_DR folder). exo generated from the fist bit file didnt seem to show any progress although snap application streamed data when exo generated from the sec bit file was downloaded.
but we dont know that what part of the code was excluded or included to generate these bit files, as documentation doesnt mention anything about them.

i hope u will understand the problem n respond soon.

[jhenderson]

The DR Framework Logic is not compatible with ISE v7.1, per the info in the post at http://www.iidsp.com/forum/viewtopic.php?t=372. You must upgrade to the latest toolset. We cannot support any but the latest version of the tools.