jhenderson
Site Admin
Joined: 07 Mar 2006
Posts: 2267
Location: So. Cal. USA
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 Posted: Thu May 07, 2009 3:34 pm Post subject: Trigger determinicity |
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| Quote: | We are having some issues where the Data entering the DAC Interface IP on all our channels are aligned, but when looking at the DAC outputs, sometime the outputs of DAC0 are skewed from DAC1 by a single DAC clock cycle. You can stop the stream, and reopen it (resulting in a new trigger/sync applied to the DACs), and sometimes the outputs of the DACs are aligned, sometimes they are not.
This would appear to be related to the DAC synchronization issue you described in the most recent release of the X5-TX manual, on page 92. And I was able to verify that by setting the DAC Delay setting to "1" on one of the DACs when it was skewed, I could bring them into alignment. (The manual mentions at one point changing the FIFO Offset instead - however, I was unable to get it to work, presumably because we only have a single SYNC/Trigger per operation, so once we see the problem and try to correct it, the update to the setting will never take place - reading the DAC datasheet, I would have thought setting FIFO_sync_dis would result in the FIFO Offset setting being updated immediately, but it didn't seem to have an impact).
So it would appear that what we are seeing is the issue you describe. However, you say that it's a problem at the highest update rates - we're only running the DACs at 186.67MSPS, with no interpolation, and would have thought that given we are far beneath the DACs maximum rate, that our sample rate would be considered low speed. Also, could you describe what in the DAC results in this synchronization issue - is it that one DAC may begin to read its internal FIFO later then the other DAC, or some other issue? Has there been any discussions with TI about how to get around the issue short of calibrating it out every time you start up?
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We've discussed this issue with TI and below is their response:
| Quote: | "It is normal for multiple devices to be off by +/- 1 DAC clock cycle. This is due to the FIFO elasticity and unknown relationship between CLKIN and DCLK."
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