Innovative Integration

Innovative Integration is a data acquisition company that designs embedded electronics with digital & analog interfaces and FPGAs for digital signal processing, software radio and data acquisition applications used in industrial and rugged environments.

Atropos

Precision Sampling Rate Generation and Triggering Controls with High Precision Reference


  • Atropos

Block Diagram
  • Atropos

Ruggedization Level Table
  • Ruggedization Level Table

Atropos Peripherals

Quick Specs
Part Number: 80340-0
Family: PMC/XMCe
Bus Type: PCI Express
Bus Width:
Bus Speed:
Form Factor: XMC
Interfaces:
Functions: Clock Timebase · Data Acquisition
DSP:
DSP Quantity: 0
DSP Speed (total):
FPGA: No FPGA
FPGA Size:
FPGA Quantity: 0
A/D Channels: 0
A/D Resolution:
A/D Rate:
D/A Channels: 0
D/A Resolution:
D/A Rate:
Digital IO:
Peripherals: 80181-0 · 80186-0 · 90181-0 · 80167-0 · 80172-0 · 80173-0 · 80207-0 · 80116-1 · 67057 · 67058 · 67059 · 65057 · 65036
Features
  • Clock generation and distribution
  • Four single-ended clock outputs
  • External clock/reference input
  • Low noise: 91 fs RMS jitter -162.5 dBc/Hz noise floor (fc=245.76 MHz)
  • Programmable 70.06 to 3080 MHz range
  • On-board 10 MHz, 250 ppb oscillator or
  • External frequency reference
  • Four programmable trigger outputs
  • Supports J16 triggers and local bus
  • External trigger input
  • XMC Module (75x150 mm)
  • PCI Express (VITA 42.3)
Applications
  • Sample clock generation for high speed data acquisition applications
  • Sample clock generation for multichannel systems
  • Synchronization for distributed systems
  • Timing Generation

Atropos Overview

Atropos is an XMC I/O module with precision, low-noise clock generation and distribution for data acquisition and communications timing applications. The module has four output clocks and four output triggers as well as a clock/reference input and a trigger input. The Atropos can also act as a system timing card in multi-board XMC, FMC or PCIe -based systems, providing the reference clock, sample clocks and triggering.

In the sample clock generation mode, the Atropos can generate clocks from 70.06 to 3080 MHz. All clock outputs may be referenced to an on-card 280 ppb temperature-compensated oscillator, or an external clock input.

The PLL circuit is fully programmable, providing extremely low noise clocks with 91 fs RMS jitter, -162.5 dBc/Hz noise floor (fc=245.76 MHz). The output clocks are phase aligned to within 100 ps. Each output clock is a 1 to 32 subdivision of the external clock or second- stage PLL, which may programmatically operate in either the 2370- 2630 or 2920-3080 MHz range.

Windows and Linux applications are provided that are used to configure and control all Atropos features.

Software tools for host development include C++ libraries and drivers for Windows and Linux.

©1988-2017 Innovative Integration