Innovative Integration

Innovative Integration is a data acquisition company that designs embedded electronics with digital & analog interfaces and FPGAs for digital signal processing, software radio and data acquisition applications used in industrial and rugged environments.

Digital Receiver V612

Dig Rec Overview >PC-based Instrument with 128 Channels DDC, Spectrum Analyzer and two XMC Module Sites


  • Digital Receiver V612

Block Diagram
  • Digital Receiver V612

Ruggedization Level Table
  • Ruggedization Level Table

Digital Receiver V612 Peripherals

Quick Specs
Part Number: 90614-0-L0
Family: Software
Bus Type: CompactPCI
Bus Width:
Bus Speed:
Form Factor: Stand-Alone
Interfaces:
Functions:
DSP:
DSP Quantity: 0
DSP Speed (total):
FPGA:
FPGA Size:
FPGA Quantity: 0
A/D Channels: 0
A/D Resolution:
A/D Rate:
D/A Channels: 0
D/A Resolution:
D/A Rate:
Digital IO:
Peripherals:
Features
  • Intel i7 Quad Core, 16 GB RAM, dual 10 GbE
  • Two, independent XMC module sites
  • Sustained logging rate up-to 1,300 MByte/s
  • Optional GPS 10 MHz ref clock/PPS

  • Per- XMC Module Features
  • Eight 14-bit, 250 MHz ADCs
  • Analog bandwidth: 400 MHz (AC Coupled)
  • Xilinx Virtex-6 SX475T-2 FPGA
  • Embedded power meter

  • Digital Down-Converter (DDC)
  • 128 DDC channels (8 banks x16 channels)
  • Programmable tuner: 1 - 250 MHz; resolution 0.0582 Hz
  • Programmable bandwidth: 10 - 800 KHz
  • Bandwidth 160 KHz DDC: SNR > 64 dB; SFDR > 76 dB
  • Support synchronous down-sampling on multiple channels and modules using external clock/trigger
  • Support synchronous VITA-49 timestamp on multiple modules

  • Real-Time Spectrum Analyzer
  • FFT Length: 32,768; 50% overlapped
  • Real-time Bandwidth: 100 MHz
  • Resolution Bandwidth: 3.8 KHz
  • 100% Probability of Intercept: 393 μsec
Applications
  • GSM
  • Digital Beamforming
  • Real-Time Spectrum Analysis

Digital Receiver V612 Overview

The V612 Digital Receiver supports one or two plug-in X6-250M modules, each providing up to 128 independent channels of DDC and one spectrum analyzer embedded in a Xilinx Virtex-6 FPGA. It supports monitoring and/or recording of wide- or narrow-band spectra or channelized IF band data. The receiver supports contiguous recording at 1,300 MByte/s with four SSDs until running out of disk space.

Eight DDC banks, each supporting 16 channels, support monitoring of 128 DDC channels per single module. Each DDC bank can select its own ADC and decimation rate; each DDC channel has its own programmable tuner and programmable low-pass filtering supporting output bandwidth up-to 800 KHz. The data is packetized in VITA-49 format with accurate timestamps, synchronous to an external PPS signal. An embedded, digital power meter monitors the power (dBm) of any ADC input, supporting analog gain control of optional, user- supplied external front-end devices.

The spectrum analyzer, which supports windowing, calculates the wide-band spectrum of raw ADC data or the narrow-band spectrum of the cooked DDC output data at a programmable update rate. A programmable peak hold feature may be enabled to latch transient activity in the spectrum and the programmable threshold monitoring spectrum feature tracks spectral activities of up-to 512 bins.

A development kit is available to support creation of custom instrumentation. Users can insert custom-made VHDL cores into the supplied Framework to create advanced applications.

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