Innovative Integration

Innovative Integration is a data acquisition company that designs embedded electronics with digital & analog interfaces and FPGAs for digital signal processing, software radio and data acquisition applications used in industrial and rugged environments.

Digital Receiver V613

Dig Rec Overview >PC-based Instrument with 8 Channels DDC, Spectrum Analyzer and Two XMC Module Sites

  • Digital Receiver V613

Block Diagram
  • Digital Receiver V613

Ruggedization Level Table
  • Ruggedization Level Table

Digital Receiver V613 Peripherals

Quick Specs
Part Number: 90615-0-L0
Family: Software
Bus Type: CompactPCI
Bus Width:
Bus Speed:
Form Factor: Stand-Alone
DSP Quantity: 0
DSP Speed (total):
FPGA Size:
FPGA Quantity: 0
A/D Channels: 0
A/D Resolution:
A/D Rate:
D/A Channels: 0
D/A Resolution:
D/A Rate:
Digital IO:
  • Intel i7 Quad Core, 16 GB RAM, dual 10 GbE
  • Two independent XMC module sites
  • Sustained logging rate up-to 1,300 MByte/s
  • Optional GPS 10 MHz ref clock/PPS

  • Per- XMC Module Features
  • Two 12-bit, 1.8 GHz ADCs
  • Analog bandwidth: 2.2 GHz (AC Coupled)
  • Xilinx Virtex-6 SX475T-2 FPGA
  • Embedded power meter

  • Digital Down-Converter (DDC)
  • Eight independent 16-bit DDC channels
  • Programmable tuner: 1 MHz – 1.8 GHz; resolution 0.4191 Hz
  • Programmable bandwidth: 10 KHz – 90 MHz
  • Bandwidth 10 MHz DDC: SNR > 58 dB; SFDR > 68 dB
  • Support synchronous down-sampling on multiple channels and modules using external clock/trigger
  • Support synchronous VITA-49 timestamp on multiple modules

  • Real-Time Spectrum Analyzer
  • FFT Length: 32,768; 50% overlapped
  • Real-time Bandwidth: 100 MHz
  • Resolution Bandwidth: 3.4 KHz
  • 100% Probability of Intercept: 437 μsec
  • Digital Receiver
  • Real-Time Spectrum Analysis
  • Surveillance
  • Software Defined Radio

Digital Receiver V613 Overview

The V613 Digital Receiver supports one or two plug-in X6-GSPS modules, each providing up to eight independent channels of DDC and one spectrum analyzer embedded in a Xilinx Virtex-6 FPGA. It supports monitoring and/or recording of wide- or narrow-band spectra or channelized IF band data. The receiver supports contiguous recording at 1,300 MByte/s with four SSDs until running out of disk space.

Each DDC has its own programmable tuner, programmable low- pass filtering, gain control, and decimation setting, supporting independent output bandwidth up-to 90 MHz. Data is packetized in VITA-49 format with accurate timestamps, synchronous to an external PPS signal. Each DDC channel can be enabled or disabled on the fly to save host storage and bandwidth. The embedded power meter monitors the power (dBm) of the ADC inputs, supporting analog gain control of optional, user-supplied external front-end devices.

The spectrum analyzer, which supports windowing, calculates the wide-band spectrum of raw ADC data or the narrow-band spectrum of the cooked DDC output data at a programmable update rate. A programmable peak hold feature may be enabled to latch transient activity in the spectrum and the programmable threshold monitoring spectrum feature tracks spectral activities of up-to 512 bins.

A development kit is available to facilitate custom designs. Users can insert custom-made cores within the provided Framework to create more advanced applications, including features such as demodulation, decoding and error correction.

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