Innovative Integration

Innovative Integration is a data acquisition company that designs embedded electronics with digital & analog interfaces and FPGAs for digital signal processing, software radio and data acquisition applications used in industrial and rugged environments.

FMC-QSFP+

FMC Module with Dual QSFP+ Ports


  • FMC-QSFP+

Block Diagram
  • FMC-QSFP+

Ruggedization Level Table
  • Ruggedization Level Table

FMC-QSFP+ Peripherals

Quick Specs
Part Number: 80289-0
Family: FMC
Bus Type: FMC
Bus Width:
Bus Speed:
Form Factor: FMC
Interfaces: SFP
Functions: Data Acquisition
DSP:
DSP Quantity: 0
DSP Speed (total):
FPGA: No FPGA
FPGA Size:
FPGA Quantity: 0
A/D Channels: 0
A/D Resolution:
A/D Rate:
D/A Channels: 0
D/A Resolution:
D/A Rate:
Digital IO:
Peripherals:
Features
  • Two QSFP+ ports
  • Up to 40 Gbps per port (IEEE 802.3ba)
  • 2-wire I2C communication interface and other low-speed electrical interface compliant to SFF 8436 and QSFP Multisource Agreement (MSA)
  • Programmable low jitter clock supports 0.16 to 350 MHz range with 1PPM step
  • Spread-spectrum clock support
  • 10 MHz, 0.5 PPM reference
  • FMC (ANSI/VITA57) Module
    (Note: module extends beyond FMC form-factor on the face plate. See mechanical requirements.)
Applications
  • Remote Radio Head receiver
  • OBSAI and CPRI interface
  • Serial FPDP and SRIO fiber optic ports

FMC-QSFP+ Overview

FMC-QSFP+ provides two QSFP+ ports on a standard FMC module with programmable clock and support features. Fiber optic links to remote IO, such as Remote Radio Head applications, from host processing and FPGA cards support up to 40 Gbps bit rates.

The QSFP+ ports are compatible with SFF-8436 transceivers, supporting both copper and fiber optic links. The two ports are fully independent on the module. QSFP+ control and monitoring signals are mapped to the FMC interface for I2C control port, power mode, reset, presence of cable, and Interrupt events.

A flexible reference clock for on the FMC-QSFP+ is fully programmable over the 0.16 to 350 MHz range. The clock can be programmed for all common rates for standards such as OC-12, OBSAI, CPRI, GbE, sFPDP and SONET. The clock has jitter performance of less than 1 ps RMS max, allowing it to meet the most stringent requirements for these applications. An on-card 10MHz Oscillator with 0.5 PPM stability is used as the PLL reference.

The FMC-QSFP+ is fully electrically compatible with FMC (ANSI/VITA 57) specifications for IO module. Mechanically, the module will fit FMC sites, however the QSFP+ connectors protrude slightly past the face of the bezel. The module is compatible with FMC HPC sites. The module consumes <750 mW exclusive of QSFP+ modules.

The FMC is provided with VHDL code illustrating the interfaces. Specific FPGA and platform support is provided for Innovative's VPX- COP and PEX-COP FPGA cards.

Software libraries and examples for C++ host development are provided. Application examples demonstrating the module features are provided for Innovative Integration platforms in for Windows, Linux and VxWorks.

©1988-2017 Innovative Integration