Innovative Integration

Innovative Integration is a data acquisition company that designs embedded electronics with digital & analog interfaces and FPGAs for digital signal processing, software radio and data acquisition applications used in industrial and rugged environments.

LVDT-Servo

4 Channels LVDT Signal Conditioner and Embedded Servo Controller


  • LVDT-Servo

Block Diagram
  • LVDT-Servo

Ruggedization Level Table
  • Ruggedization Level Table

LVDT-Servo Peripherals

Quick Specs
Part Number: 90627-0-L0
Family: System on a Chip
Bus Type:
Bus Width: 32-bits
Bus Speed: 1 GHz
Form Factor: Stand-Alone
Interfaces: Ethernet · USB · FMC · eMMC
Functions:
DSP: ARM Cortex-A9
DSP Quantity: 2
DSP Speed (total):
FPGA: Zynq Z7045
FPGA Size: 350K Logic Cells/900 DSP Slices
FPGA Quantity: 1
A/D Channels: 0
A/D Resolution:
A/D Rate:
D/A Channels: 0
D/A Resolution:
D/A Rate:
Digital IO:
Peripherals:
Features
  • Xilinx Zynq Z7045 with dual ARM Cortex-A9 CPU, 1 GB RAM, running PetaLinux
  • Eight 16-bit ADC and eight 16-bit DAC sampling synchronously at 400 KHz, DC-coupled
  • USB 2.0 x1, 1 GbE x1, 32 GB eMMC, JTAG
  • Internal 14-bit GPIO and UART x2
  • Self-bootable standalone operation
  • Optional support for IEEE-1588 network or
  • GPS-synchronized timing

  • LVDT Signal Conditioner
  • Four independent LVDT signal conditioners
  • Offset/Phase (16-bit, unipolar or bipolar) to CPU
  • at 5 KSPS per channel
  • Null point calibration
  • LVDT demodulator latency:
  • Excitation frequency > 1.61 KHz: 950 us
  • Excitation frequency < 1.59 KHz: 2.7 ms
  • Excitation frequency range: 400 Hz – 1.59 KHz; 1.61 KHz – 20 KHz and higher; max: 195 KHz

  • Embedded Servo Loop
  • Software or Firmware Servo Loop for minimum latency
  • Development Kit available Software: C++, Malibu Library Firmware: VHDL/Xilinx Sysgen/HLS

LVDT-Servo Overview

LVDT-Servo is a turnkey instrument combining Innovative’s Cardsharp single board computer, FMC-Servo I/O module plus custom firmware and software to perform 4 channels of LVDT synchronous, simultaneous demodulation and control.

The digital demodulation core provides sharp digital low-pass filtering and rapid phase tracking on the delta phase of the excitation and return signal. Built-in null point calibration efficiently solves the offset error around the null point. The powerful hardware platform supports a wide range of excitation frequencies from 400 Hz to 20 KHz, with latency of less than 2.7 ms.

The Xilinx Zynq Z7045 FPGA is available for custom, real-time servo loop core implementations. Build the algorithm in VHDL, Xilinx System Generator and MATLAB, or Xilinx High Level Synthesizer (HLS) running inside the FPGA. Then, run a C++ program as the servo loop running in bare-metal in CPU core 1.

ZYNQ Diagram

Synchronize to an unlimited number of LVDT-Servo signal conditioners by applying the same external clock and external trigger to the FMC-Servo front panel connector.

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