Innovative Integration

Innovative Integration is a data acquisition company that designs embedded electronics with digital & analog interfaces and FPGAs for digital signal processing, software radio and data acquisition applications used in industrial and rugged environments.

PEX6-COP

PCI Express Desktop/Server Coprocessor with Virtex6 FPGA computing core and FMC IO site


  • PEX6-COP

Block Diagram
  • PEX6-COP

Ruggedization Level Table
  • Ruggedization Level Table

PEX6-COP Peripherals

Quick Specs
Part Number: 80284-0-L0 · 80284-2-L0
Family: Solomente
Bus Type: PCI Express
Bus Width:
Bus Speed:
Form Factor: Half-length Desktop PCI
Interfaces:
Functions: Bus Adapter · FPGA
DSP:
DSP Quantity: 0
DSP Speed (total):
FPGA: Virtex-6
FPGA Size:
FPGA Quantity: 0
A/D Channels: 0
A/D Resolution:
A/D Rate:
D/A Channels: 0
D/A Resolution:
D/A Rate:
Digital IO:
Peripherals: 80259-0
Features
  • Desktop/Server 3/4-length FPGA coprocessor card
  • FMC I/O site (VITA 57) with x10 5 Gbps MGT lanes, 80 LVDS pairs (LA, HA, HB full support)
  • FPGA Computing Core
  • Xilinx Virtex6 LX240T, SX315T or SX475T
  • 5 Banks of 256MB x 16 DDR3 (2.5GB total)
  • 2 banks of QDRII+ SRAM (4MB each, options to 18MB each)
  • 32Mb FLASH
  • Dual sample clock inputs
  • High speed trigger inputs support multi-card synchronization and coordinated sampling
  • Gen2 x8 PCI Express providing 4 GB/s burst and 3.2 GB/s sustained transfer rates
  • x4 Secondary Port usable as PCI Express or Aurora
  • <15W typical excluding FMC
  • Configures from on-card FLASH
  • Temperature monitoring
  • High temperature option: 0° to +85°C operation
Applications
  • Wireless Receivers - LTE, WiMAX, SATCOM
  • RADAR
  • Signal Intelligence
  • Medical Imaging
  • High Speed Data Recording and Playback
  • IP development

PEX6-COP Overview

The PEX6-COP is a flexible FPGA co-processor card that integrates a Virtex6 FPGA computing core with an industry-standard FMC IO module on a half-length PCI Express desktop or server card.

The FPGA computing core features the Xilinx Virtex 6 FPGA family, in densities up to LX550 and SX475. The SX475 provides over 2000 DSP MAC elements operating at up to 500 MHz. The FPGA core has two 9MB QDRII+ SRAM banks and three 256MB LPDDR3 DRAM banks. Each memory is directly connected to the FPGA and is fully independent.

For system communications, the PEX6-COP has a PCI Express and a secondary x4 port. The PCIe port is a x8, Gen2 interface capable of up to 3.2 GB/s sustained operation with 4 GB/s burst rate. The secondary port can be used as Aurora ports (x4 to x1), as a second PCI Express x4 port, or using a custom protocol.

An FMC site, conforming to VITA 57, provides configurable IO for the PEX6-COP. The FMC site has full support for the high pin count connector, with over 80 LVDS pairs directly connected to the FPGA and x10 lanes at up to 6.25 Gbps per lane. FMC also is readily adapted to application-specific custom modules.

The PEX-COP family power is less than 15W for typical operation. The card is available rated for wide-temperature (-40 to 85C) and 100% humidity with conformal coating.

The FPGA logic can be fully customized using the Frame Work Logic tool set. The toolset provides support for both MATLAB and RTL designs. The MATLAB BSP supports real-time hardware-in-the-loop development using the graphical, block diagram Simulink environment with Xilinx System Generator. IP cores for a range of signal processing cores for applications such as wireless, RADAR and SIGINT such as DDC, demodulation, and FFT are also available.

Software tools for host development include C++ libraries and drivers for VxWorks, Windows and Linux. Application examples demonstrating the module features are provided.

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