A16D2 Auto Muxing FAQ

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A16D2 Auto Muxing FAQ

Postby jhenderson » Wed Mar 29, 2006 10:18 am


Setting bit X in this registers enables automatic multiplexing on the A16D2. When active, the analog multiplexer which drives the A/D automatically indexes through consecutive, contiguously numbered input channels. Thus, data samples sequentially read from the A/D device during data acquisition correspond to voltages present on a contiguous range of channels, rather than a single channel.

The multiplexer initially routes the analog input from channel zero to the A/D converter. Contiguous, ascending-numbered channels are subsequently sampled. The final channel sampled is specified by the Mux End register.

As the multiplexer switches between channels, the analog filter which resides between the multiplexer and the A/D converter within the signal path will be presented with rapidly slewing input voltages. Consequently, it is essential that the analog input filter be disabled when automatic multiplexing is used to avoid analog cross-talk.

Note: It is imperative that the A/D converter sample results be read within the conversion sample interval, to avoid channel swapping. For example, when sampling at 50 kHz, the conversion sample period is 20 uS. Failure to consistently read the A/D sample results within this time period will induce a “channel swap”, which will render the data acquisition sequence unusable. To mitigate this possibility, use of a DMA channel to service the A.D converter is recommended.

Recommending Programming Initialization Sequence
Use the following sequence for Auto Muxing:
- Write the gain mode for each channel (Gain Array registers).
- Write the number of channels to scan (Mux End register).
- Turn on the auto mux mode.
- Turn off the filter.
- Enable the timebase.


The contents of this register are significant only when bit X within the Auto Mux Enable register is set.

This register should be loaded with the number analog input channels which are to be contiguously sampled during automatic multiplexing, minus one.


The contents of this register are significant only when bit X within the Auto Mux Enable register is set.

Each time the multiplexer indexes to a new channel, the programmable gain amplifier (PGA) is automatically set to operate in a new gain mode. So, each analog input channel may operate in a unique gain mode during automatic multiplexing.

To control the gain mode corresponding to each multiplexed channel, an array of sixteen, 2-bit registers (the Gain Array list) must be initialized. Each register within the Gain Array list corresponds to the gain mode for a single multiplexed channel. For example, Gain Array register zero controls the PGA gain mode which becomes active when sampling analog input channel zero. Similarly, Gain Array register one controls the PGA gain mode when sampling analog input channel one.

When initializing the Gain Array list, all sixteen registers must be updated, regardless of the setting of the Mux End register.

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