Hardware solutions for radar applications are more complex than ever. Increasing complexity in modulation and transmission schemes, new frequency bands, and varying solution objectives create a challenge in finding the right balance of tradeoffs.

Innovative Integration’s radar hardware solutions use a modular approach to radar applications. We start with a host computer or embedded SoC card that houses building blocks of either XMC or FMC slots. The computers contain the latest FPGA processing chips on the market, going all the way up to a Xilinx Ultrascale plus chip.

  • The XU-AWG is an XMC module which features two AC-coupled single-ended 16-bit DAC outputs with programmable DC bias. The DAC devices employed support synchronization, interpolation, and their unique output circuits allow improved frequency synthesis in the 2nd Nyquist zone. This can shift the Nyquist null frequency in the output spectrum to two times the typical Nyquist null frequency. The maximum sample rate of the DAC IC is 12 GSPS, the maximum external direct clocking rate is 6 GSPS and the on board PLL can generate clocks up to 4.8 GHz. The DACs' JESD 204B interfaces can stream data with transfer rates up to 6 GSPS.
  • The XA-AWG is an XMC IO module featuring eight 16-bit, 300 MSPS DAC channels designed for high speed arbitrary waveform generation, wireless transmission, and RADAR pulse generation applications.
  • The X6-1000M integrates high-speed digitizing and signal generation with signal processing on a PMC/XMC IO module for demanding DSP applications. The tight coupling of the digitizing to the Virtex6 FPGA core realizes architectures for SDR, RADAR, and LIDAR front end sensor digitizing and processing. The PCI Express system interface sustains transfer rates over 2 GB/s for data recording and integration as part of a high performance realtime system.
  • The X6-400M integrates high speed digitizing and signal generation with signal processing on a PMC/XMC IO module with a powerful Xilinx Virtex 6 FPGA signal processing core, and high performance PCI Express/PCI host interface.
  • The X6-250M integrates digitizing with signal processing on a PMC/XMC IO module. The module has a powerful Xilinx Virtex 6 FPGA signal processing core, and high performance PCI Express/PCI host interface. Applications include software-defined radio, RADAR receivers, and multi-channel data recorders. The X6-250M has eight simultaneously sampling A/D channels that sample at rates up to 250 MSPS (14-bit). The A/D have matched input delays and response. The A/D are supported by a programmable sample clock PLL and triggering that support multi-card synchronization for large scale systems.
  • The X3-Servo module features 12 simultaneously sampling A/D and DACs with an FPGA computing core. Low latency SAR A/D and fast-settling DACs support real-time servo control applications. The programmable input range and high input interface directly to many sensors, while the output is capable of driving many transducers. Front panel digital IO can be also be used as PWM or process controls.
  • The X3-SDF is an XMC IO module featuring 4 simultaneously sampling, sigma delta A/D channels designed for vibration, acoustic and high dynamic range measurements. The A/D device has programmable output rates up to 24 bits @ 2.5 MSPS and 16- bits @ 20 MSPS using the programmable filter in the A/D.
  • The X3-DIO is a PCI Express XMC IO module for high speed digital IO data interfaces featuring 64bits of front-panel digital IO. The digital IO is either single-ended LVCMOS or LVDS differential pairs that is directly connected to the FPGA, for applications such as high speed pattern generation, digital recording, custom IO interfaces and controls.
  • The X3-A4D4 is an XMC IO module featuring four 16-bit, 4 MSPS A/D channels and four 16-bit, 50 MSPS DAC channels with FPGA computing core designed for servo controls, arbitrary waveform generation and stimulusresponse applications. Low latency SAR A/D and no-pipeline DACs support real-time servo control applications. Flexible trigger methods include counted frames, software triggering and external triggering. The sample rate clock is either an external clock or on-board programmable PLL clock source. Data acquisition control, signal processing, buffering, and system interface functions are implemented in a Xilinx Spartan3A DSP, 1.8M gate device. Two 1Mx16 memories are used for data buffering and FPGA computing memory.
  • The X3-25M is an XMC IO module featuring two 16-bit, 105 MSPS A/D channels and two 16-bit, 50 MSPS DAC channels designed for high speed stimulus-response, ultrasound, and servo control applications.
  • The FMC-SERVO module features eight simultaneously sampling A/D and DACs with an FPGA computing core. Low latency SAR A/D and fast-settling DACs support real-time servo control applications. The programmable input range and high input interface directly to many sensors, while the output is capable of driving many transducers. Front panel digital IO can be also be used as PWM or process controls.
  • The FMC-SDF module features four simultaneously sampling ADCs and a dual output DAC. High resolution sigma-delta ADCs and high resolution DACs support high dynamic range applications such as audio, ATE, and seismic data acquisition.