Two 160 MSPS 16-bit ADC & Two 615 MSPS 16-bit DAC & Artix-7 FPGA

The XA-160M is an XMC IO module featuring two 16-bit, 160 MSPS A/D channels and two 16-bit, 615 MSPS DAC channels designed for high speed stimulus-response, ultrasound, and servo control applications.

Flexible trigger methods include counted frames, software triggering and external triggering. The sample rate clock is either an external clock or on- board programmable PLL clock source.



  • Two 160 MSPS, 16-bit ADC channels
  • Two 615 MSPS, 16-bit DAC channels
  • 89 dB SFDR, 72 dBFS SNR A/Ds
  • 73 dB SFDR, 68 dBFS SNR D/As
  • 2.4Vpp input range
  • 1Vpp output range
  • DIO on P16 (19 differential pairs)
  • Xilinx Artix-7 FPGA
  • DDR3 Memory
  • Programmable or external sample clock
  • Synchronized system sampling using
  • Common reference clock and triggers
  • Framed, software or external triggering
  • Log acquisition timing and events
  • Power management features
  • PCI Express 2.0 XMC Module (75×150 mm)
  • Use in any PCI Express desktop, compact PCI/PXI, PXIe, or cabled PCI Express application


  • Stimulus-response measurements
  • High speed servo controls
  • Arbitrary Waveform Generation
  • Optical Servo
  • Medical Scanning
  • Download Datasheet PDF

Data acquisition control, signal processing, buffering, and system interface functions are implemented in a Xilinx Artix-7 FPGA device. Two 256Mx16 memories provide data buffering and FPGA computing memory.

The logic can be fully customized using VHDL and MATLAB using the FrameWork Logic toolset. The MATLAB BSP supports real-time hardware-in-the- loop development using the graphical, block diagram Simulink environment with Xilinx System Generator.

The PCI Express 2.0 interface supports continuous data rates up to 1600 MB/ s between the module and the host. A flexible data packet system implemented over the PCIe interface provides both high data rates to the host that is readily expandable for custom applications.

Block Diagram

XA-160M Block Diagram

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