Innovative Integration

Innovative Integration is a data acquisition company that designs embedded electronics with digital & analog interfaces and FPGAs for digital signal processing, software radio and data acquisition applications used in industrial and rugged environments.

Digital Receiver V614

Dig Rec Overview > PC-based Instrument with Single Ultra-Wideband DDC, Spectrum Analyzer and Two XMC Module Sites

  • Digital Receiver V614

Block Diagram
  • Digital Receiver V614

Ruggedization Level Table
  • Ruggedization Level Table

Digital Receiver V614 Peripherals

Quick Specs
Part Number: 90616-0-L0
Family: Software
Bus Type: CompactPCI
Bus Width:
Bus Speed:
Form Factor: Stand-Alone
DSP Quantity: 0
DSP Speed (total):
FPGA Size:
FPGA Quantity: 0
A/D Channels: 0
A/D Resolution:
A/D Rate:
D/A Channels: 0
D/A Resolution:
D/A Rate:
Digital IO:
  • Intel i7 Quad Core, 16 GB RAM, dual 10 GbE
  • Two, independent XMC module sites
  • Sustained logging rate up-to 1,300 MByte/s
  • Optional GPS 10 MHz ref clock/PPS

  • Per- XMC Module Features
  • Two 12-bit, 1.8 GHz ADCs
  • Analog bandwidth: 2.2 GHz (AC Coupled)
  • Xilinx Virtex-6 SX475T-2 FPGA
  • Embedded power meter

  • Digital Down-Converter (DDC)
  • Single 8-bit DDC channel
  • Programmable tuner: 1 MHz – 1.8 GHz; resolution 0.4191 Hz
  • Programmable bandwidth: 60 – 750 MHz
  • Bandwidth 500 MHz DDC: SNR > 42 dB; SFDR > 64 dB
  • Support synchronous down-sampling on multiple channels and modules using external clock/trigger
  • Support synchronous VITA-49 timestamp on multiple modules

  • Spectrum Analyzer
  • FFT Length: 32,768; 0% overlapped
  • Fast-Attack/Slow-Decay
  • Programmable Windowing
  • Digital Receiver
  • Spectrum Analysis
  • Surveillance
  • Software Defined Radio

Digital Receiver V614 Overview

The V614 Digital Receiver supports one or two plug-in X6-GSPS XMC modules, each featuring one ultra-wideband DDC and one spectrum analyzer embedded in the Xilinx Virtex-6 FPGA. It supports monitoring and/or recording of wide- or narrow-band spectra or channelized IF band data. The receiver supports contiguous recording at 1,300 MByte/s with four SSDs until running out of disk space.

The DDC has its own programmable tuner, programmable low-pass filtering, gain control, and decimation settings, supporting output bandwidth up-to 750 MHz. Data is packetized in VITA-49 format with accurate timestamps, synchronous to an external PPS signal. Each DDC channel can be enabled and disabled on the fly to conserve host computer storage and bandwidth. An embedded power meter monitors the power (dBm) of the ADC inputs, supporting analog gain control of optional, user-supplied external front-end devices.

The spectrum analyzer, including windowing, calculates the wide- band spectrum of the ADC data or the narrow-band spectrum of the DDC output data at the programmable update rate. The maximum hold helps to retain the information in the spectrum and the programmable threshold monitoring spectrum detects the spectral activities up-to 512 bins.

A development kit is available to facilitate custom designs. Users can insert custom-made cores within the provided Framework to create more advanced applications, including features such as demodulation, decoding and error correction.

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