Innovative Integration

Innovative Integration is a data acquisition company that designs embedded electronics with digital & analog interfaces and FPGAs for digital signal processing, software radio and data acquisition applications used in industrial and rugged environments.


PCI Express XMC Module with 12 simultaneous channels of 10 MSPS 16-bit A/D, and 1.8M FPGA with DSP

  • X3-2M

Block Diagram
  • X3-2M

Ruggedization Level Table
  • Ruggedization Level Table

X3-2M Peripherals

Quick Specs
Part Number: 80248-0
Family: PMC/XMCe
Bus Type: PCI Express
Bus Width: VITA
Bus Speed: 42.3
Form Factor: XMC
Functions: Data Acquisition · DSP - Digital Signal Processor · FPGA
DSP Quantity: 0
DSP Speed (total):
FPGA: Spartan-3A
FPGA Size:
FPGA Quantity: 1
A/D Channels: 0
A/D Resolution:
A/D Rate:
D/A Channels: 0
D/A Resolution:
D/A Rate:
Digital IO:
Peripherals: 80181-0 · 80186-0 · 90181-0 · 80167-0 · 80172-0 · 80173-0 · 80207-0 · 80116-1 · 67057 · 67058 · 67059 · 65057 · 65036 · 67102
  • 12 channels of 10 MSPS, 16-bit simultaneously sampling A/D
  • -110 dB noise floor, 91 dB SFDR
  • Low latency SAR converters
  • 50 ohm, differential inputs
  • Continuously acquire 12 simultaneous channels at 10 MSPS to system memory
  • Stream to system memory at up to 220MB/s
  • Xilinx Spartan3A DSP, 1.8M gate FPGA
  • 4MB SRAM
  • Sample clock is external or programmable, low jitter PLL
  • Framed, software or external triggering
  • Log acquisition timing and events
  • 6 LVDS digital IO pairs on Front Panel
  • 44 bits digital IO on P16
  • Power Management features
  • PCI Express XMC Module (75x150 mm)
  • Use in any PCI Express desktop, compact PCI/PXI, or cabled PCI Express application
  • Multichannel sensor interface
  • Neuro-physical instrumentation

X3-2M Overview

The X3-2M is a PCI Express XMC IO module featuring 12 simultaneously sampling 16-bit, 10 MSPS A/D channels and an FPGA processing core. It is designed for high speed instrumentation and analysis for neuro-physical, RADAR, and high speed data acquisition applications.

Flexible trigger methods include counted frames, software triggering and external triggering. The sample rate clock is either an external clock or on-board programmable PLL clock source.

Data acquisition control, signal processing, buffering, and system interface functions are implemented in a Xilinx Spartan3A DSP FPGA, 1.8M gate device. Two 512Kx32 memory devices are used for data buffering and FPGA computing memory.

The logic can be fully customized using VHDL and MATLAB using the FrameWork Logic toolset. The MATLAB BSP supports real-time hardware-in-the-loop development using the graphical, block diagram Simulink environment with Xilinx System Generator.

The PCI Express interface supports continuous data rates up to 220 MB/ s between the module and the host. A flexible data packet system implemented over the PCIe interface provides both high data rates to the host that is readily expandable for custom applications.

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