Innovative Integration

Innovative Integration is a data acquisition company that designs embedded electronics with digital & analog interfaces and FPGAs for digital signal processing, software radio and data acquisition applications used in industrial and rugged environments.

XA-160M

PCI Express XMC Module with Two 160 MSPS A/Ds, Two 615 MSPS DACs and Artix-7 FPGA


  • XA-160M

Block Diagram
  • XA-160M

Ruggedization Level Table
  • Ruggedization Level Table

XA-160M Peripherals

Quick Specs
Part Number: 80362
Family: PMC/XMCe
Bus Type: PCI Express
Bus Width: 8-lane
Bus Speed:
Form Factor: XMC
Interfaces:
Functions: FPGA
DSP:
DSP Quantity: 0
DSP Speed (total):
FPGA: Artix-7
FPGA Size:
FPGA Quantity: 1
A/D Channels: 2
A/D Resolution: 16-bit
A/D Rate: b0160 MSPS
D/A Channels: 2
D/A Resolution: 16-bit
D/A Rate: b0615 MSPS
Digital IO:
Peripherals:
Features
  • Two 160 MSPS, 16-bit ADC channels
  • Two 615 MSPS, 16-bit DAC channels
  • 89 dB SFDR, 72 dBFS SNR A/Ds
  • 73 dB SFDR, 68 dBFS SNR D/As
  • 2.4Vpp input range
  • 1Vpp output range
  • DIO on P16 (19 differential pairs)
  • Xilinx Artix-7 FPGA
  • DDR3 Memory
  • Programmable or external sample clock
  • Synchronized system sampling using
  • common reference clock and triggers
  • Framed, software or external triggering
  • Log acquisition timing and events
  • Power management features
  • PCI Express 2.0 XMC Module (75x150 mm)
  • Use in any PCI Express desktop, compact PCI/PXI, PXIe, or cabled PCI Express application
Applications
  • Stimulus-response measurements
  • High speed servo controls
  • Arbitrary Waveform Generation
  • RADAR
  • LIDAR
  • Optical Servo
  • Medical Scanning

XA-160M Overview

The XA-160M is an XMC IO module featuring two 16-bit, 160 MSPS A/D channels and two 16-bit, 615 MSPS DAC channels designed for high speed stimulus-response, ultrasound, and servo control applications.

Flexible trigger methods include counted frames, software triggering and external triggering. The sample rate clock is either an external clock or on- board programmable PLL clock source.

Data acquisition control, signal processing, buffering, and system interface functions are implemented in a Xilinx Artix-7 FPGA device. Two 256Mx16 memories provide data buffering and FPGA computing memory.

The logic can be fully customized using VHDL and MATLAB using the FrameWork Logic toolset. The MATLAB BSP supports real-time hardware-in-the- loop development using the graphical, block diagram Simulink environment with Xilinx System Generator.

The PCI Express 2.0 interface supports continuous data rates up to 1600 MB/ s between the module and the host. A flexible data packet system implemented over the PCIe interface provides both high data rates to the host that is readily expandable for custom applications.

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