Innovative Integration

Innovative Integration is a data acquisition company that designs embedded electronics with digital & analog interfaces and FPGAs for digital signal processing, software radio and data acquisition applications used in industrial and rugged environments.

XA-RX

PCI Express XMC Module with eight 125 MSPS A/Ds and Artix-7 FPGA


  • XA-RX

Block Diagram
  • XA-RX

Ruggedization Level Table
  • Ruggedization Level Table

XA-RX Peripherals

Quick Specs
Part Number: 80371
Family: PMC/XMCe
Bus Type: PCI Express
Bus Width: 8-lane
Bus Speed:
Form Factor: XMC
Interfaces:
Functions: FPGA
DSP:
DSP Quantity: 0
DSP Speed (total):
FPGA: Artix-7
FPGA Size:
FPGA Quantity: 1
A/D Channels: 8
A/D Resolution: 16-bit
A/D Rate: b0125 MSPS
D/A Channels: 0
D/A Resolution:
D/A Rate:
Digital IO:
Peripherals:
Features
  • Eight 125 MSPS, 16-bit ADC channels
  • 83 dB SFDR, 77 dBFS SNR A/Ds
  • 1.3Vpp input range
  • DIO on P16 (19 differential pairs)
  • Xilinx Artix-7 FPGA
  • DDR3 Memory
  • Programmable or external sample clock
  • Synchronized system sampling using common reference clock and triggers
  • Framed, software or external triggering
  • Log acquisition timing and events
  • Power management features
  • PCI Express 2.0 XMC Module (75x150 mm)
  • Use in any PCI Express desktop, compact PCI/PXI, PXIe, or cabled PCI Express application
Applications
  • High speed imaging
  • Medical ultrasound and MRI
  • Quadrature radio receivers
  • Diversity radio receivers
  • Test equipment

XA-RX Overview

The XA-RX is an XMC IO module featuring eight 16-bit, 125 MSPS A/D channels designed for High speed imaging, medical ultrasound and MRI, quadrature radio receivers, diversity radio receivers, test equipment.

Flexible trigger methods include counted frames, software triggering and external triggering. The sample rate clock is either an external clock or on-board programmable PLL clock source.

Data acquisition control, signal processing, buffering, and system interface functions are implemented in a Xilinx Artix-7 FPGA device. Two 256Mx16 memories provide data buffering and FPGA computing memory.

The logic can be fully customized using VHDL and MATLAB using the FrameWork Logic toolset. The MATLAB BSP supports real-time hardware-in-the-loop development using the graphical, block diagram Simulink environment with Xilinx System Generator.

The PCI Express 2.0 interface supports data rates up to 1600 MB/s for unbuffered continuous data or bursty data streams. When using a standard configuration involving DDR3 buffered data, a continuous data rate up to 1300 MB/s is supported.

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